公开(公告)号：US12249598B2

公开(公告)日：2025-03-11

申请号：US17862277

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L25/18 ,  G11C5/02 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/065 ,  H10B12/00

Abstract: Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

公开(公告)号：US11348871B2

公开(公告)日：2022-05-31

申请号：US16742305

申请日：2020-01-14

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/31 ,  H01L23/053 ,  H01L23/29 ,  H01L23/538 ,  H01L21/56 ,  H01L21/04 ,  H01L21/768 ,  H01L23/00 ,  H01L21/8239

Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

公开(公告)号：US10978484B2

公开(公告)日：2021-04-13

申请号：US16848718

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L27/088 ,  H01L27/1159 ,  H01L27/108 ,  H01L27/11507 ,  H01L27/11592 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  G11C11/22

Abstract: In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.

公开(公告)号：US10790288B2

公开(公告)日：2020-09-29

申请号：US15809710

申请日：2017-11-10

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L27/108 ,  H01L27/11507 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12

Abstract: Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.

公开(公告)号：US10784264B2

公开(公告)日：2020-09-22

申请号：US16213172

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200185370A1

公开(公告)日：2020-06-11

申请号：US16213257

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L25/18 ,  H01L23/528 ,  H01L27/108 ,  H01L23/522 ,  G11C11/4091 ,  G11C11/408 ,  H01L23/544 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

公开(公告)号：US10607923B1

公开(公告)日：2020-03-31

申请号：US16213362

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L23/48 ,  H01L23/528 ,  G11C11/408 ,  H01L27/108 ,  H01L25/18 ,  H01L25/065 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having a conductive line supported by a deck and extending along a longitudinal direction. The conductive line is configured to carry an electrical signal. A connection region is along the conductive line. The conductive line splits amongst multiple components as it passes through the connection region. The components are spread-apart from one another along a lateral direction which is orthogonal to the longitudinal direction. An opening extends vertically through the deck and through the connection region. The opening breaks one of the components of the conductive line to leave another of the components to carry the electrical signal across the connection region.

公开(公告)号：US20200052097A1

公开(公告)日：2020-02-13

申请号：US16551495

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L29/66 ,  H01L29/04 ,  H01L27/108 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10424656B2

公开(公告)日：2019-09-24

申请号：US15598894

申请日：2017-05-18

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/78 ,  H01L29/04

Abstract: Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190067195A1

公开(公告)日：2019-02-28

申请号：US16010734

申请日：2018-06-18

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/53295 ,  H01L27/115

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.