公开(公告)号：US11886348B2

公开(公告)日：2024-01-30

申请号：US18117820

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Laurent Isenegger ,  Robert M. Walker ,  Cagdas Dirik

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0683 ,  G06F12/0835 ,  G06F2212/283

Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

公开(公告)号：US20230098454A1

公开(公告)日：2023-03-30

申请号：US17485060

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert M. Walker ,  Laurent Isenegger

IPC: G06F3/06

Abstract: A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

公开(公告)号：US11442867B2

公开(公告)日：2022-09-13

申请号：US16228336

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Laurent Isenegger ,  Dhawal Bavishi ,  Jeffrey Frederiksen

IPC: G06F12/0879 ,  G06F12/12

Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

公开(公告)号：US12254213B2

公开(公告)日：2025-03-18

申请号：US17558465

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Laurent Isenegger ,  Robert Walker

IPC: G06F3/06 ,  G06F12/02

Abstract: Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US11836096B2

公开(公告)日：2023-12-05

申请号：US17559320

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Robert Walker ,  Laurent Isenegger

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F9/30101 ,  G06F13/1621 ,  G06F13/1642 ,  G06F13/4221

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US11809710B2

公开(公告)日：2023-11-07

申请号：US17485060

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert M. Walker ,  Laurent Isenegger

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

公开(公告)号：US20230060874A1

公开(公告)日：2023-03-02

申请号：US17463995

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Kirthi Ravindra Kulkarni ,  Laurent Isenegger

IPC: G06F13/16

Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.

公开(公告)号：US11301383B2

公开(公告)日：2022-04-12

申请号：US16928999

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Cagdas Dirik ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F12/0806

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

公开(公告)号：US20250014628A1

公开(公告)日：2025-01-09

申请号：US18886542

申请日：2024-09-16

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jeffrey L. Scott ,  Laurent Isenegger ,  Robert M. Walker

IPC: G11C11/406 ,  G06F13/16

Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

公开(公告)号：US20230205701A1

公开(公告)日：2023-06-29

申请号：US18117820

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Laurent Isenegger ,  Robert M. Walker ,  Cagdas Dirik

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F3/06

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F3/0683 ,  G06F3/061 ,  G06F3/0658 ,  G06F2212/283

Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.