公开(公告)号：US08949582B2

公开(公告)日：2015-02-03

申请号：US13687911

申请日：2012-11-28

Applicant: LSI Corporation

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog ,  Te Khac Ma ,  Steven J. Pollock

IPC: G06F9/455 ,  G06F9/46 ,  H04L29/06 ,  H04L12/933 ,  G06F15/167 ,  H04L12/931

CPC classification number: H04L69/22 ,  G06F15/167 ,  H04L47/2441 ,  H04L49/00 ,  H04L49/101 ,  H04L49/109 ,  H04L49/506

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

Abstract translation: 描述的实施例对由网络处理器接收的分组进行分类。 网络处理器的处理模块生成与每个接收的分组相对应的任务。 分组分类处理器独立于接收到的任务的流标识符来确定对应于每个任务的控制数据。 多线程指令引擎处理对应于接收到的任务的指令的线程，每个任务对应于网络处理器的分组流，并且维护每个流程的线程状态表和序列计数器。 活动线程由线程状态表跟踪，每个状态条目包括序列值和标识流的流值。 每个序列计数器通过在每次针对关联流程的线程的处理开始时递增序列计数器来生成每个线程的序列值，并且每当关联的流程的线程完成时递减序列计数器。

公开(公告)号：US20130089099A1

公开(公告)日：2013-04-11

申请号：US13687958

申请日：2012-11-28

Applicant: LSI Corporation

Inventor： Steven J. Pollock ,  Deepak Mital ,  James T. Clee

IPC: H04L12/56

CPC classification number: H04L47/6205 ,  G06F15/167 ,  H04L47/2441 ,  H04L47/621 ,  H04L49/00 ,  H04L49/101 ,  H04L49/109 ,  H04L49/506

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows. The modified packets are queued for transmission as an output packet of the network processor.

Abstract translation: 描述的实施例对由网络处理器接收的分组进行分类。 网络处理器的处理模块生成与每个接收的分组相对应的任务。 调度器生成对应于分组分类处理器从相应处理模块接收到的任务的上下文，每个上下文对应于给定的流，并且将每个上下文存储在调度器的相应的每流先进先出缓冲器中。 分组修改器基于指令的线程生成修改的分组，每个指令线程对应于从调度器接收的上下文。 修改的分组在排队分组以便发送之前被生成，作为网络处理器的输出分组，并且分组修改器以按照每个流生成上下文的顺序处理用于生成修改的分组的指令，而不用行头 流动之间阻塞。 修改的分组被排队等待作为网络处理器的输出分组传输。

公开(公告)号：US20150091620A1

公开(公告)日：2015-04-02

申请号：US14045295

申请日：2013-10-03

Applicant: LSI Corporation

Inventor： Steven J. Pollock

IPC: H03K17/16

CPC classification number: H03K23/667

Abstract: An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.

Abstract translation: 一种装置包括无毛刺分频器和无毛刺多路复用器。 无毛刺除法器可以被配置为响应于从第一源接收的分频器值和时钟信号而产生第一系统时钟。 分频值以预定的步数从第一值改变到第二值。 无毛刺多路复用器可以被配置为响应于控制信号在所述第一系统时钟和第二系统时钟之间进行选择。

公开(公告)号：US20130089098A1

公开(公告)日：2013-04-11

申请号：US13687911

申请日：2012-11-28

Applicant: LSI Corporation

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog ,  Te Khac Ma ,  Steven J. Pollock

IPC: H04L29/06

CPC classification number: H04L69/22 ,  G06F15/167 ,  H04L47/2441 ,  H04L49/00 ,  H04L49/101 ,  H04L49/109 ,  H04L49/506

Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

Abstract translation: 描述的实施例对由网络处理器接收的分组进行分类。 网络处理器的处理模块生成与每个接收的分组相对应的任务。 分组分类处理器独立于接收到的任务的流标识符来确定对应于每个任务的控制数据。 多线程指令引擎处理对应于接收到的任务的指令的线程，每个任务对应于网络处理器的分组流，并且维护每个流程的线程状态表和序列计数器。 活动线程由线程状态表跟踪，每个状态条目包括序列值和标识流的流值。 每个序列计数器通过在每次针对关联流程的线程的处理开始时递增序列计数器来生成每个线程的序列值，并且每当关联的流程的线程完成时递减顺序计数器。