公开(公告)号：US12131637B2

公开(公告)日：2024-10-29

申请号：US17705766

申请日：2022-03-28

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa

IPC: G08G1/0967 ,  G06T7/70 ,  G06V20/58 ,  G08G1/01 ,  G08G1/04 ,  G08G1/137

CPC classification number: G08G1/0967 ,  G06T7/70 ,  G06V20/58 ,  G08G1/0112 ,  G08G1/0141 ,  G08G1/04 ,  G08G1/096716 ,  G08G1/096741 ,  G08G1/096775 ,  G08G1/137 ,  G06T2207/30261

Abstract: A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. The server generates list information including the target information the first and second monitoring devices, and transmits the list information to the first and second monitoring devices. The first controller further generates a map according to the list information received from the server, and displays the map on the first display.

公开(公告)号：US11941251B2

公开(公告)日：2024-03-26

申请号：US17982840

申请日：2022-11-08

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Masanobu Shirakawa ,  Kiyotaka Iwasaki

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

公开(公告)号：US11875063B2

公开(公告)日：2024-01-16

申请号：US18082759

申请日：2022-12-16

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Tsukasa Tokutomi

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C11/5621 ,  G11C11/5671 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

公开(公告)号：US11869601B2

公开(公告)日：2024-01-09

申请号：US18053271

申请日：2022-11-07

Applicant: Kioxia Corporation

Inventor： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H10B69/00

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H10B69/00

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US11804267B2

公开(公告)日：2023-10-31

申请号：US17852683

申请日：2022-06-29

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Kenta Yasufuku ,  Akira Yamaga

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3427 ,  G11C16/3459 ,  G11C11/5642 ,  G11C2211/5641

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

公开(公告)号：US11790986B2

公开(公告)日：2023-10-17

申请号：US17874926

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C11/00 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C16/30 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C2211/563 ,  G11C2211/5642 ,  H10B43/27 ,  H10B43/35

Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

公开(公告)号：US11756642B2

公开(公告)日：2023-09-12

申请号：US17476229

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

CPC classification number: G11C29/12 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0673 ,  G11C16/08 ,  G11C16/26 ,  G11C2029/1202

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

公开(公告)号：US11705204B2

公开(公告)日：2023-07-18

申请号：US17585370

申请日：2022-01-26

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  H10B43/27 ,  H10B43/35 ,  G11C16/3445

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US11537465B2

公开(公告)日：2022-12-27

申请号：US17174399

申请日：2021-02-12

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Masamichi Fujiwara ,  Kazumasa Yamamoto ,  Naoaki Kokubun ,  Tatsuro Hitomi ,  Hironori Uchikawa

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US11513735B2

公开(公告)日：2022-11-29

申请号：US17190496

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Yasuhiko Kurosawa ,  Naomi Takeda ,  Masanobu Shirakawa ,  Yasuyuki Ushijima ,  Shinichi Kanno

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.