公开(公告)号：US08552776B2

公开(公告)日：2013-10-08

申请号：US13364198

申请日：2012-02-01

Applicant: Jongtae Kwak ,  Kallol Mazumder

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/00

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

公开(公告)号：US08093937B2

公开(公告)日：2012-01-10

申请号：US12620041

申请日：2009-11-17

Applicant: Jongtae Kwak ,  Kang Yong Kim

Inventor： Jongtae Kwak ,  Kang Yong Kim

IPC: H03L7/06 ,  H03K5/159

CPC classification number: H03L7/00 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract translation: 时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和细微延迟的边界处实现了平滑的相位转变。 该系统可以使用单个粗延迟线，其被配置为从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差。 粗延迟线可以具有分层结构或非分层结构。 相位混合器接收这两个中间时钟，并产生在中间时钟的相位之间具有相位的最终输出时钟。 在高时钟频率下延迟线中的粗略移位不影响馈送到相位混频器中的中间时钟之间的相位关系。 来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。

公开(公告)号：US07973577B2

公开(公告)日：2011-07-05

申请号：US12432267

申请日：2009-04-29

Applicant: Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

Inventor： Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

Abstract translation: 本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。 具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点 朝向VDL的左侧（或最大延迟）边缘）。 这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。 其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。 此外，当使用所公开的技术时，可以完全省去缓冲阶段。 另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

公开(公告)号：US07656745B2

公开(公告)日：2010-02-02

申请号：US11724910

申请日：2007-03-15

Applicant: Jongtae Kwak

Inventor： Jongtae Kwak

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  H03K3/012 ,  H03K3/0375 ,  H03L7/0814 ,  H03L7/181

Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

Abstract translation: 描述了具有时钟同步电路和读等待时间控制电路的读等待时间控制电路。 时钟同步电路包括可调延迟线，以产生其相位与输入时钟信号的相位同步的输出时钟信号。 读等待时间控制电路相对于输入时钟信号的定时捕获读指令信号，并相对于输出时钟信号的定时输出读指令信号，使得输出指示读指令的读命令信号。

公开(公告)号：US07554375B2

公开(公告)日：2009-06-30

申请号：US11843371

申请日：2007-08-22

Applicant: Jongtae Kwak

Inventor： Jongtae Kwak

IPC: H03H11/26

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K19/01707 ,  H03K19/01721 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03K2005/00215

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract translation: 描述包括时钟混合电路以提供可选择的传播时间的延迟电路。 来自混合电路的输出信号通过可变延迟线选择性耦合，以同步两个时钟信号。

公开(公告)号：US07541851B2

公开(公告)日：2009-06-02

申请号：US11608903

申请日：2006-12-11

Applicant: Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

Inventor： Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

Abstract translation: 本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。 具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点 朝向VDL的左侧（或最大延迟）边缘）。 这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。 其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。 此外，当使用所公开的技术时，可以完全省去缓冲阶段。 另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

公开(公告)号：US20060267648A1

公开(公告)日：2006-11-30

申请号：US11136893

申请日：2005-05-25

Applicant: Jongtae Kwak

Inventor： Jongtae Kwak

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K19/01707 ,  H03K19/01721 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03K2005/00215

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

公开(公告)号：US20130342254A1

公开(公告)日：2013-12-26

申请号：US13531341

申请日：2012-06-22

Applicant: Kallol Mazumder ,  Jongtae Kwak ,  Tsugio Takahashi ,  Yasuo Satoh

Inventor： Kallol Mazumder ,  Jongtae Kwak ,  Tsugio Takahashi ,  Yasuo Satoh

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

Abstract translation: 公开了与调整信号路径的最小前向路径延迟相关的装置和方法。 一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。 一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大 比所选延迟的最大计数值。

公开(公告)号：US08587354B2

公开(公告)日：2013-11-19

申请号：US13171755

申请日：2011-06-29

Applicant: Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

Inventor： Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

公开(公告)号：US20130194013A1

公开(公告)日：2013-08-01

申请号：US13364198

申请日：2012-02-01

Applicant: Jongtae Kwak ,  Kallol Mazumder

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/18

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract translation: 公开了与改变用于执行命令的命令信号的定时相关的装置和方法。 一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加 。 时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。