公开(公告)号：US20120079248A1

公开(公告)日：2012-03-29

申请号：US12890292

申请日：2010-09-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jason Brandt

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jason Brandt

IPC: G06F9/30 ,  G06F9/22

CPC classification number: G06F9/384 ,  G06F9/226 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/4484

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

Abstract translation: 一个方面的装置包括多个微码别名位置和微码存储器。 微代码子程序的微指令存储在微代码存储器中。 微指令具有微代码位置的指示。 微码子程序的微代码调用者也存储在微代码存储器中。 微代码调用者可操作地指定由微代码子程序的微指令指示的微代码别名位置中的参数的位置。 该装置还包括与微码别名位置耦合的参数位置确定逻辑。 参数位置确定逻辑可操作以响应于微代码子程序的微指令，从微指令接收微码别名位置的指示，并确定由微指令指示的微码别名位置中指定的参数的位置。

公开(公告)号：US20120166766A1

公开(公告)日：2012-06-28

申请号：US12978471

申请日：2010-12-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam

IPC: G06F9/28 ,  G06F9/30

CPC classification number: G06F9/28 ,  G06F9/26 ,  G06F9/262 ,  G06F9/30

Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In one embodiment, the stacks are invisible to software. In an embodiment, a microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit are generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation. Other embodiments are also claimed and disclosed.

Abstract translation: 描述了用于增强的微代码地址堆栈指针操纵的方法和装置。 在一个实施例中，堆栈对于软件是不可见的。 在一个实施例中，微代码指令指针（UIP）和在微代码存储单元中要访问的下一个地址基于微操作的操作码，标记和UIP堆栈地址生成。 可以基于微操作的信号和立即字段来生成UIP堆栈地址。 还要求和公开其它实施例。

公开(公告)号：US09329865B2

公开(公告)日：2016-05-03

申请号：US13915227

申请日：2013-06-11

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

IPC: G06F21/74 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30054 ,  G06F9/30101 ,  G06F9/384

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract translation: 处理器包括微代码存储器，用于存储第一微代码子程序和第一微代码子程序的微代码调用程序。 处理器还包括包括第一多个微代码别名位置的第一微代码别名存储器和包括第二多个微代码别名位置的第二微码别名存储器。 处理器还包括耦合到第一微代码存储器和第二微代码别名存储器的第一逻辑，其中第一逻辑被配置为选择第一微代码别名存储器中的第一逻辑，用于存储一个参数位置 或b）第二微代码别名存储器，用于存储第二多个微码别名位置之一中的参数位置。

公开(公告)号：US08793469B2

公开(公告)日：2014-07-29

申请号：US12971819

申请日：2010-12-17

Applicant: Kameswar Subramaniam ,  Anthony Wojciechowski ,  Jonathan D. Combs

Inventor： Kameswar Subramaniam ,  Anthony Wojciechowski ,  Jonathan D. Combs

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/30178

Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.

Abstract translation: 公开了一种计算机，电路和计算机可读介质。 在一个实施例中，处理器包括指令解码器单元，其可以用一组数据字段将宏指令解码为至少一个微操作。 所得到的微操作具有至少一个处于压缩形式的数据字段。 指令译码器单元具有可以利用压缩形式数据字段存储微操作的存储器。 指令解码器单元还具有提取逻辑，其能够将压缩形式的数据字段提取为未压缩形式的数据字段。 提取后，指令译码器单元也可以将所提取的未压缩形式数据字段的微操作发送到执行单元。 计算机还包括能够执行发送的微操作的执行单元。

公开(公告)号：US20120159129A1

公开(公告)日：2012-06-21

申请号：US12971819

申请日：2010-12-17

Applicant: Kameswar Subramaniam ,  Anthony Wojciechowski ,  Jonathan D. Combs

Inventor： Kameswar Subramaniam ,  Anthony Wojciechowski ,  Jonathan D. Combs

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/30178

Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.

Abstract translation: 公开了一种计算机，电路和计算机可读介质。 在一个实施例中，处理器包括指令解码器单元，其可以用一组数据字段将宏指令解码为至少一个微操作。 所得到的微操作具有至少一个处于压缩形式的数据字段。 指令译码器单元具有可以利用压缩形式数据字段存储微操作的存储器。 指令解码器单元还具有提取逻辑，其能够将压缩形式的数据字段提取为未压缩形式的数据字段。 提取后，指令译码器单元也可以将所提取的未压缩形式数据字段的微操作发送到执行单元。 计算机还包括能够执行发送的微操作的执行单元。

公开(公告)号：US20120079237A1

公开(公告)日：2012-03-29

申请号：US12890335

申请日：2010-09-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam

IPC: G06F9/22 ,  G06F9/30

CPC classification number: G06F9/26 ,  G06F9/3016

Abstract: An apparatus of one aspect includes a microcode storage, a microcode subroutine stored in the microcode storage, and a microcode caller of the microcode subroutine stored in the microcode storage. The microcode caller has a save microinstruction that indicates a destination storage location. The apparatus also includes microcode alias locations. Each of the microcode alias locations is operable to store a value. The value in the microcode alias location corresponds to a parameter passed between the microcode caller and the microcode subroutine. The apparatus includes save logic coupled with the microcode alias locations to receive the values from the microcode alias locations. The save logic is operable, responsive to the save microinstruction, to save the values from the microcode alias locations in the destination storage location indicated by the save microinstruction.

Abstract translation: 一个方面的装置包括微代码存储器，存储在微代码存储器中的微代码子程序，以及存储在微代码存储器中的微代码子程序的微代码调用者。 微代码调用者具有指示目的地存储位置的保存微指令。 该装置还包括微码别名位置。 每个微码别名位置可操作以存储值。 微码别名位置中的值对应于在微代码调用者和微代码子例程之间传递的参数。 该装置包括与微码别名位置相结合的保存逻辑以从微代码别名位置接收值。 保存逻辑可操作以响应于保存微指令，以从存储微指令指示的目的地存储位置中的微代码别名位置中保存值。

公开(公告)号：US20140365754A1

公开(公告)日：2014-12-11

申请号：US13915227

申请日：2013-06-11

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam ,  Jeffrey G. Wiedemeier

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30101 ,  G06F9/384

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract translation: 处理器包括微代码存储器，用于存储第一微代码子程序和第一微代码子程序的微代码调用程序。 处理器还包括包括第一多个微代码别名位置的第一微代码别名存储器和包括第二多个微代码别名位置的第二微码别名存储器。 处理器还包括耦合到第一微代码存储器和第二微代码别名存储器的第一逻辑，其中第一逻辑被配置为选择第一微代码别名存储器中的第一逻辑，用于存储一个参数位置 或b）第二微代码别名存储器，用于存储第二多个微码别名位置之一中的参数位置。

公开(公告)号：US08832419B2

公开(公告)日：2014-09-09

申请号：US12978471

申请日：2010-12-24

Applicant: Jonathan D. Combs ,  Kameswar Subramaniam

Inventor： Jonathan D. Combs ,  Kameswar Subramaniam

IPC: G06F9/28 ,  G06F9/30

CPC classification number: G06F9/28 ,  G06F9/26 ,  G06F9/262 ,  G06F9/30

Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In some examples, the stacks are invisible to software. A microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit may be generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation.

Abstract translation: 描述了用于增强的微代码地址堆栈指针操纵的方法和装置。 在一些示例中，堆栈对于软件是不可见的。 可以基于微操作的操作码，标记和UIP堆栈地址来生成微码指令指针（UIP）和要在微代码存储单元中访问的下一个地址。 可以基于微操作的信号和立即字段来生成UIP堆栈地址。

公开(公告)号：US20140223141A1

公开(公告)日：2014-08-07

申请号：US13997789

申请日：2011-12-29

Applicant: Jonathan D. Combs ,  Jason W. Brandt ,  Benjamin C. Chaffin ,  Julio Gago ,  Andrew F. Glew

Inventor： Jonathan D. Combs ,  Jason W. Brandt ,  Benjamin C. Chaffin ,  Julio Gago ,  Andrew F. Glew

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F9/3851 ,  G06F12/0842 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/657

Abstract: In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.

Abstract translation: 在一些实现中，处理器可以包括诸如翻译后备缓冲器的数据结构，其包括包含具有虚拟地址的第一映射信息和与第一线程相关联的第一上下文的条目。 控制逻辑可以接收对具有虚拟地址的第二映射信息和与第二线程相关联的第二上下文的请求。 控制逻辑可以确定与第二上下文相关联的第二映射信息是否等于数据结构条目中的第一映射信息。 如果第二映射信息等同于第一映射信息，则控制逻辑可以将第二线程与数据结构条目中包含的第一映射信息相关联，以共享第一线程和第二线程之间的条目。

公开(公告)号：US09811338B2

公开(公告)日：2017-11-07

申请号：US13976261

申请日：2011-11-04

Applicant: Jonathan D. Combs ,  Jason W. Brandt ,  Robert Valentine

Inventor： Jonathan D. Combs ,  Jason W. Brandt ,  Robert Valentine

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30094 ,  G06F9/30185

Abstract: In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.