公开(公告)号：US20100214849A1

公开(公告)日：2010-08-26

申请号：US12647725

申请日：2009-12-28

Applicant: Hyun Jong Jin ,  Jin Haeng Lee

Inventor： Hyun Jong Jin ,  Jin Haeng Lee

IPC: G11C16/06 ,  G11C7/10

CPC classification number: G11C7/1033 ,  G11C7/065 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.

Abstract translation: 当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果 使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果 当执行第一验证操作时。

公开(公告)号：US07730272B2

公开(公告)日：2010-06-01

申请号：US11753359

申请日：2007-05-24

Applicant: Jin Haeng Lee

Inventor： Jin Haeng Lee

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F21/79

Abstract: A non-volatile memory device includes an input/output terminal mixing section configured to couple data input/output terminals of the memory device to data input/output terminals of a page buffer in accordance with a user selection. A user data authenticating section is configured to transmit a control signal to the input/output terminal mixing section so that the input/output terminal mixing section couples the data input/output terminals of the memory device to the data input/output terminals of the page buffer in accordance with the user selection. A spare cell is configured to store the coupling configuration of the data input/output terminals of the memory device and the data input/output terminals of the page buffer in accordance with the user selection.

Abstract translation: 非易失性存储器件包括：输入/输出端混合部分，被配置为根据用户选择将存储器件的数据输入/输出端子耦合到页缓冲器的数据输入/输出端。 用户数据认证部被配置为将控制信号发送到输入/输出端混合部分，使得输入/输出端混合部分将存储器件的数据输入/输出端子耦合到页的数据输入/输出端子 缓冲器根据用户选择。 备用单元被配置为根据用户选择存储存储器件的数据输入/输出端子和页缓冲器的数据输入/输出端子的耦合配置。

公开(公告)号：US08335107B2

公开(公告)日：2012-12-18

申请号：US12971208

申请日：2010-12-17

Applicant: Jin Haeng Lee

Inventor： Jin Haeng Lee

IPC: G11C16/00

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3404

Abstract: A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.

Abstract translation: 半导体存储器件包括具有耦合到多个位线的多个存储器单元的存储器块，耦合到感测节点并被配置为存储要被编程到存储器单元中的数据的第一锁存器组，其中存储器单元耦合到 位线，并且感测节点耦合到位线中的至少一个，耦合到感测节点并被配置为接收第一锁存器组的数据的第二锁存器组，以及感测节点电压控制电路，被配置为控制 根据存储在第一锁存器组中的数据的感测节点。

公开(公告)号：US20130083600A1

公开(公告)日：2013-04-04

申请号：US13619122

申请日：2012-09-14

Applicant: Jin Haeng Lee

Inventor： Jin Haeng Lee

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C8/04 ,  G11C8/12 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

Abstract: A method of operating a semiconductor device includes selecting one of a plurality of memory cell blocks included in a memory cell array, programming even-numbered memory cells coupled to a selected word line among the word lines of the selected memory cell block, programming odd-numbered memory cells coupled to the selected word line, programming odd-numbered memory cells coupled to a next word line adjacent to the selected word line, and programming even-numbered memory cells coupled to the next word line, wherein the programming is repeated until programming on selected memory cells coupled to all the word lines of the selected memory cell block is completed.

Abstract translation: 一种操作半导体器件的方法包括选择包括在存储单元阵列中的多个存储单元块中的一个，对所选择的存储单元块的字线中耦合到所选字线的偶数存储单元进行编程， 耦合到所选字线的编号的存储器单元，编程耦合到与所选字线相邻的下一个字线的奇数编号的存储器单元，以及编程耦合到下一个字线的偶数存储单元，其中重复编程直到编程 在与所选存储单元块的所有字线耦合的选定存储单元上完成。

公开(公告)号：US08189394B2

公开(公告)日：2012-05-29

申请号：US12647725

申请日：2009-12-28

Applicant: Hyun Jong Jin ,  Jin Haeng Lee

Inventor： Hyun Jong Jin ,  Jin Haeng Lee

IPC: G11C16/06

CPC classification number: G11C7/1033 ,  G11C7/065 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.

Abstract translation: 当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果 使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果 当执行第一验证操作时。

公开(公告)号：US20080162851A1

公开(公告)日：2008-07-03

申请号：US11753359

申请日：2007-05-24

Applicant: Jin Haeng Lee

Inventor： Jin Haeng Lee

IPC: G06F12/00

CPC classification number: G06F21/79

Abstract: A non-volatile memory device includes an input/output terminal mixing section configured to couple data input/output terminals of the memory device to data input/output terminals of a page buffer in accordance with a user selection. A user data authenticating section is configured to transmit a control signal to the input/output terminal mixing section so that the input/output terminal mixing section couples the data input/output terminals of the memory device to the data input/output terminals of the page buffer in accordance with the user selection. A spare cell is configured to store the coupling configuration of the data input/output terminals of the memory device and the data input/output terminals of the page buffer in accordance with the user selection.

Abstract translation: 非易失性存储器件包括：输入/输出端混合部分，被配置为根据用户选择将存储器件的数据输入/输出端子耦合到页缓冲器的数据输入/输出端。 用户数据认证部被配置为将控制信号发送到输入/输出端混合部分，使得输入/输出端混合部分将存储器件的数据输入/输出端子耦合到页的数据输入/输出端子 缓冲器根据用户选择。 备用单元被配置为根据用户选择存储存储器件的数据输入/输出端子和页缓冲器的数据输入/输出端子的耦合配置。