公开(公告)号：US20080063128A1

公开(公告)日：2008-03-13

申请号：US11651323

申请日：2007-01-09

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H03D3/24

CPC classification number: H03D13/004

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

Abstract translation: 一种用于有效支持数据传输过程的系统和方法包括：具有相位检测器的锁相环，该相位检测器比较时钟信号和输入数据，以产生用于调节从压控振荡器产生的时钟信号的相位误差信号。 相位检测器包括上升沿检测器电路，其生成边缘检测信号P以指示输入数据中是否存在数据转换。 相位检测器还包括一个引导/延迟指示器电路，其生成引导/延迟指示符信号T以指示时钟信号相对于输入数据是早还是晚。

公开(公告)号：US08680927B2

公开(公告)日：2014-03-25

申请号：US13068761

申请日：2011-05-19

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H03F3/08

CPC classification number: H03F3/08 ,  H03G3/3084

Abstract: An apparatus for implementing a front end circuit for a transimpedance amplifier includes a front end core that receives an input signal from a photo diode. The front end core responsively generates a balanced output signal to downstream devices. A power supply provides a supply voltage to the front end circuit. In accordance with the present invention, a current source is located between the supply voltage the front end core to thereby isolate the front end core from disturbances on the power supply. This biasing arrangement advantageously provides an improved power supply rejection ratio for the front end circuit.

Abstract translation: 用于实现跨阻放大器的前端电路的装置包括从光电二极管接收输入信号的前端芯。 前端核心响应地产生到下游设备的平衡输出信号。 电源为前端电路提供电源电压。 根据本发明，电流源位于前端磁芯的电源电压之间，从而将前端磁芯与电源上的干扰隔离。 该偏置装置有利地为前端电路提供了改进的电源抑制比。

公开(公告)号：US08633776B2

公开(公告)日：2014-01-21

申请号：US11903710

申请日：2007-09-24

Applicant: Jeremy Chatwin ,  Bernard J. Griffiths

Inventor： Jeremy Chatwin ,  Bernard J. Griffiths

IPC: H03B5/08 ,  H03B5/18

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H04L7/0004 ,  H04L7/033

Abstract: A system and method for effectively performing a clock signal distribution procedure includes a clock generator configured to generate one or more clock signals that include electronic timing information. A clock load utilizes the electronic timing information from the clock signals to synchronize appropriate system processes. Capacitive coupling means are provided in a series configuration for transferring the clock signals from the clock generator to the clock load in accordance with an alternating-current direct-drive technique.

Abstract translation: 一种用于有效执行时钟信号分配过程的系统和方法包括被配置为产生包括电子定时信息的一个或多个时钟信号的时钟发生器。 时钟负载利用来自时钟信号的电子定时信息来同步适当的系统过程。 按照交流直接驱动技术，串联配置电容耦合装置用于将时钟信号从时钟发生器传送到时钟负载。

公开(公告)号：US08314660B2

公开(公告)日：2012-11-20

申请号：US13065723

申请日：2011-03-29

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H03F3/08

CPC classification number: H04L25/0272 ,  H04B10/11 ,  H04B10/693 ,  H04L25/028

Abstract: An apparatus and method for effectively implementing a unit Gm cell includes an input P that receives an input P signal and an input N that receives an input N signal. The unit Gm cell further includes an output P that generates an output P signal that is connected through a first bias resistor to the input N. The unit Gm cell also includes an output N that generates an output N signal that is connected through a second bias resistor to the input P. The unit Gm cell features level-shifting resistors that cause the output P signal and the output N signal to be at different respective voltage levels. A Vcore supply voltage may thus be reduced by a voltage potential across the level-shifting resistors to operate the unit Gm cell with a reduced Vcore supply voltage.

Abstract translation: 用于有效实现单元Gm单元的装置和方法包括接收输入P信号的输入端P和接收输入N信号的输入端N. 单元Gm单元还包括产生通过第一偏置电阻器连接到输入端N的输出P信号的输出P.单元Gm单元还包括产生通过第二偏置连接的输出N信号的输出N 电阻到输入P.单元Gm单元具有电平移动电阻，其使得输出P信号和输出N信号处于不同的相应电压电平。 因此，Vcore电源电压可以通过电平移动电阻两端的电压降低，以便以降低的Vcore电源电压来操作单元Gm单元。

公开(公告)号：US07817764B2

公开(公告)日：2010-10-19

申请号：US11731292

申请日：2007-03-30

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0814 ,  H04L7/0338

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase interpolator with a modular array of unit phase interpolators that each receives a respective input clock signal that is phase-shifted with respect to other input clock signals received by the remaining unit phase interpolators. The unit phase interpolators responsively generate corresponding UPI output signals that are summed together to produce a receiver clock signal. The phase interpolator receives a phase control word that includes a UPI selection segment and a UPI output-control segment. The phase interpolator utilizes the UPI selection segment to selectively activate pairs of the unit phase interpolators. The phase interpolator also utilizes the UPI output-control segment for controlling the UPI output signals to thereby adjust phase characteristics of the receiver clock signal.

Abstract translation: 一种用于有效支持数据传输过程的系统和方法包括具有单位相位内插器的模块阵列的相位内插器，每个相位内插器接收相对于由剩余单位相位内插器接收的其它输入时钟信号相移的相应输入时钟信号 。 单位相位内插器响应地产生相加的UPI输出信号，其被相加在一起以产生接收机时钟信号。 相位插值器接收包括UPI选择段和UPI输出控制段的相位控制字。 相位插值器利用UPI选择段来选择性地激活单相内插器的对。 相位插值器还利用UPI输出控制段来控制UPI输出信号，从而调整接收机时钟信号的相位特性。

公开(公告)号：US20110096884A1

公开(公告)日：2011-04-28

申请号：US12927483

申请日：2010-11-16

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H04L7/02

CPC classification number: H03D13/004

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

公开(公告)号：US07864911B2

公开(公告)日：2011-01-04

申请号：US11651323

申请日：2007-01-09

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H03D3/24

CPC classification number: H03D13/004

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

Abstract translation: 一种用于有效支持数据传输过程的系统和方法包括：具有相位检测器的锁相环，该相位检测器比较时钟信号和输入数据，以产生用于调节从压控振荡器产生的时钟信号的相位误差信号。 相位检测器包括上升沿检测器电路，其生成边缘检测信号P以指示输入数据中是否存在数据转换。 相位检测器还包括一个引导/延迟指示器电路，其生成引导/延迟指示符信号T以指示时钟信号相对于输入数据是早还是晚。

公开(公告)号：US20080169849A1

公开(公告)日：2008-07-17

申请号：US11879088

申请日：2007-07-16

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H03L7/06

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H04L7/0004 ,  H04L7/033

Abstract: A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing input data and the receiver clock signal. In addition, a lock-assist circuit generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal. A loop filter performs a BPD transfer function to generate a VCO input control signal from the BPD output signal during the BPD mode. The same loop filter also performs a PFD transfer function to generate the VCO input control signal from the PFD output signal during the PFD mode.

Abstract translation: 用于有效利用双模式锁相环来支持数据传输过程的系统和方法包括压控振荡器，其产生响应于VCO输入控制信号的接收机时钟信号。 二进制相位检测器通过比较输入数据和接收机时钟信号在BPD模式下产生BPD输出信号。 此外，锁定辅助电路在PFD模式期间通过比较参考信号和分频的接收机时钟信号来产生PFD输出信号。 循环滤波器执行BPD传递函数，以在BPD模式期间从BPD输出信号生成VCO输入控制信号。 相同的环路滤波器还执行PFD传输功能，以在PFD模式期间从PFD输出信号产生VCO输入控制信号。

公开(公告)号：US20120250795A1

公开(公告)日：2012-10-04

申请号：US13066412

申请日：2011-04-14

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H04L27/00

CPC classification number: H03F3/08

Abstract: An apparatus for implementing a front end core for a transimpedance amplifier includes an input transimpedance stage that receives an FE core input signal and responsively generates an output transimpedance gain signal. A first output gain stage receives the output transimpedance gain signal and responsively generates an FE core output signal. A phase inverter stage also receives the output transimpedance gain signal and responsively generates an inverted output signal. A second output gain stage then receives the inverted output signal and responsively generates an inverted FE core output signal.

Abstract translation: 用于实现跨阻放大器的前端芯的装置包括输入跨阻抗级，其接收FE核心输入信号并且响应地产生输出跨阻增益信号。 第一输出增益级接收输出跨阻增益信号并且响应地产生FE核心输出信号。 相位反相器级还接收输出跨阻增益信号并且响应地产生反相输出信号。 然后，第二输出增益级接收反相输出信号并且响应地产生反相的FE核心输出信号。

公开(公告)号：US20120250794A1

公开(公告)日：2012-10-04

申请号：US13065723

申请日：2011-03-29

Applicant: Jeremy Chatwin

Inventor： Jeremy Chatwin

IPC: H04L27/00

CPC classification number: H04L25/0272 ,  H04B10/11 ,  H04B10/693 ,  H04L25/028

Abstract: An apparatus and method for effectively implementing a unit Gm cell includes an input P that receives an input P signal and an input N that receives an input N signal. The unit Gm cell further includes an output P that generates an output P signal that is connected through a first bias resistor to the input N. The unit Gm cell also includes an output N that generates an output N signal that is connected through a second bias resistor to the input P. The unit Gm cell features level-shifting resistors that cause the output P signal and the output N signal to be at different respective voltage levels. A Vcore supply voltage may thus be reduced by a voltage potential across the level-shifting resistors to operate the unit Gm cell with a reduced Vcore supply voltage.

Abstract translation: 用于有效实现单元Gm单元的装置和方法包括接收输入P信号的输入端P和接收输入N信号的输入端N. 单元Gm单元还包括产生通过第一偏置电阻器连接到输入端N的输出P信号的输出P.单元Gm单元还包括产生通过第二偏置连接的输出N信号的输出N 电阻到输入P.单元Gm单元具有电平移动电阻，其使得输出P信号和输出N信号处于不同的相应电压电平。 因此，Vcore电源电压可以通过电平移动电阻两端的电压降低，以便以降低的Vcore电源电压来操作单元Gm单元。