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    Bypass and insertion algorithms for exclusive last-level caches
    1.
    发明授权
    Bypass and insertion algorithms for exclusive last-level caches 有权
    独占的最后一级缓存的旁路和插入算法

    公开(公告)号：US08667222B2

    公开(公告)日：2014-03-04

    申请号：US13078415

    申请日：2011-04-01

    Applicant: Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney

    Inventor： Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney

    IPC: G06F12/00

    CPC classification number: G06F12/0888 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128

    Abstract: An apparatus and method are described for implementing an exclusive lower level cache (LLC) policy within a computer processor. For example, one embodiment of a computer processor comprises: a mid-level cache circuit (MLC) for storing a first set of cache lines containing instructions and/or data; a lower level cache circuit (LLC) for storing a second set of cache lines of instructions and/or data; and an insertion circuit for implementing a policy for inserting or replacing cache lines within the LLC based on values of use recency and use frequency associated with the lines.

    Abstract translation: 描述了用于在计算机处理器内实现专用低级缓存（LLC）策略的装置和方法。 例如，计算机处理器的一个实施例包括：用于存储包含指令和/或数据的第一组高速缓存行的中级高速缓存电路（MLC）; 用于存储第二组指令和/或数据的高速缓存行的低级缓存电路（LLC）; 以及插入电路，用于基于与线路相关联的使用新近度和使用频率的值来实现用于在LLC内插入或替换高速缓存线的策略。

    BYPASS AND INSERTION ALGORITHMS FOR EXCLUSIVE LAST-LEVEL CACHES
    2.
    发明申请
    BYPASS AND INSERTION ALGORITHMS FOR EXCLUSIVE LAST-LEVEL CACHES 有权
    旁路和插入算法用于独特的最后级别的高速缓存

    公开(公告)号：US20120254550A1

    公开(公告)日：2012-10-04

    申请号：US13078415

    申请日：2011-04-01

    Applicant: Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney

    Inventor： Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney

    IPC: G06F12/08

    CPC classification number: G06F12/0888 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128

    Abstract: An apparatus and method are described for implementing an exclusive lower level cache (LLC) policy within a computer processor. For example, one embodiment of a computer processor comprises: a mid-level cache circuit (MLC) for storing a first set of cache lines containing instructions and/or data; a lower level cache circuit (LLC) for storing a second set of cache lines of instructions and/or data; and an insertion circuit for implementing a policy for inserting or replacing cache lines within the LLC based on values of use recency and use frequency associated with the lines.

    Abstract translation: 描述了用于在计算机处理器内实现专用低级缓存（LLC）策略的装置和方法。 例如，计算机处理器的一个实施例包括：用于存储包含指令和/或数据的第一组高速缓存行的中级高速缓存电路（MLC）; 用于存储第二组指令和/或数据的高速缓存行的低级缓存电路（LLC）; 以及插入电路，用于基于与线路相关联的使用新近度和使用频率的值来实现用于在LLC内插入或替换高速缓存线的策略。

    Hierarchy-aware Replacement Policy
    3.
    发明申请
    Hierarchy-aware Replacement Policy 审中-公开
    层次感知替代政策

    公开(公告)号：US20130166846A1

    公开(公告)日：2013-06-27

    申请号：US13722607

    申请日：2012-12-20

    Applicant: Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Joseph Nuzman

    Inventor： Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Joseph Nuzman

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0897 ,  G06F12/128

    Abstract: Some implementations disclosed herein provide techniques and arrangements for a hierarchy-aware replacement policy for a last-level cache. A detector may be used to provide the last-level cache with information about blocks in a lower-level cache. For example, the detector may receive a notification identifying a block evicted from the lower-level cache. The notification may include a category associated with the block. The detector may identify a request that caused the block to be filled into the lower-level cache. The detector may determine whether one or more statistics associated with the category satisfy a threshold. In response to determining that the one or more statistics associated with the category satisfy the threshold, the detector may send an indication to the last-level cache that the block is a candidate for eviction from the last-level cache.

    Abstract translation: 本文中公开的一些实施例提供了用于最后一级高速缓存的层次感知替换策略的技术和布置。 可以使用检测器来向最后一级缓存提供关于下级缓存中的块的信息。 例如，检测器可以接收识别从下级缓存中移出的块的通知。 通知可以包括与块相关联的类别。 检测器可以识别导致块被填充到下级高速缓存中的请求。 检测器可以确定与该类别相关联的一个或多个统计信息是否满足阈值。 响应于确定与类别相关联的一个或多个统计信息满足阈值，检测器可以向最后一级高速缓存发送指示该块是从最后一级高速缓存撤出的候选者的指示。

    Instruction and Logic for Managing Cumulative System Bandwidth through Dynamic Request Partitioning
    7.
    发明申请
    Instruction and Logic for Managing Cumulative System Bandwidth through Dynamic Request Partitioning 审中-公开
    通过动态请求分区管理累积系统带宽的指令和逻辑

    公开(公告)号：US20160179387A1

    公开(公告)日：2016-06-23

    申请号：US14971057

    申请日：2015-12-16

    Applicant: Jayesh Gaur ,  Prasanna Rengasamy ,  Pradeep Ramachandran ,  Sreenivas Subramoney

    Inventor： Jayesh Gaur ,  Prasanna Rengasamy ,  Pradeep Ramachandran ,  Sreenivas Subramoney

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0604 ,  G06F3/0613 ,  G06F3/0653 ,  G06F3/0671 ,  G06F12/0888

    Abstract: A processor includes an execution unit, a memory subsystem, and a memory management unit (MMU). The MMU includes logic to evaluate a first bandwidth usage of the memory subsystem and logic to evaluate a second bandwidth usage between the processor and a memory. The memory is communicatively coupled to the memory subsystem. The memory subsystem is to implement a cache for the memory. The MMU further includes logic to evaluate a request of the memory subsystem, and, based upon the first bandwidth usage and the second bandwidth usage, fulfill the request by bypassing the memory subsystem.

    Abstract translation: 处理器包括执行单元，存储器子系统和存储器管理单元（MMU）。 MMU包括评估存储器子系统的第一带宽使用和评估处理器和存储器之间的第二带宽使用的逻辑的逻辑。 存储器通信地耦合到存储器子系统。 内存子系统是为内存实现缓存。 MMU还包括评估存储器子系统的请求的逻辑，并且基于第一带宽使用和第二带宽使用，通过绕过存储器子系统来满足请求。

    ADAPTIVE ADMISSION CONTROL FOR ON DIE INTERCONNECT
    8.
    发明申请
    ADAPTIVE ADMISSION CONTROL FOR ON DIE INTERCONNECT 审中-公开
    适用于DIE互连的ADMISSION控制

    公开(公告)号：US20150188797A1

    公开(公告)日：2015-07-02

    申请号：US14142748

    申请日：2013-12-27

    Applicant: Guy Satat ,  Evgeny Bolotin ,  Julius Mandelblat ,  Jayesh Gaur ,  Supratik Majumder ,  Ravi K. Venkatesan

    Inventor： Guy Satat ,  Evgeny Bolotin ,  Julius Mandelblat ,  Jayesh Gaur ,  Supratik Majumder ,  Ravi K. Venkatesan

    IPC: H04L12/26 ,  G06F15/173

    CPC classification number: G06F15/17337 ,  G06F15/7825 ,  H04L43/0817 ,  H04L43/16 ,  H04L47/12 ,  H04L47/25

    Abstract: Methods and apparatus relating to adaptive admission control for on die interconnect are described. In one embodiment, admission control logic determines whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information. The resource utilization information is received from a plurality of resources that are shared amongst the one or more sources of data. The threshold value is determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition. Other embodiments are also disclosed.

    Abstract translation: 描述了关于管芯互连的自适应接纳控制的方法和装置。 在一个实施例中，允许控制逻辑至少部分地基于阈值和资源利用信息的比较来确定是否引起来自一个或多个数据源的请求的准入速率的改变。 从在一个或多个数据源之间共享的多个资源接收资源利用信息。 至少部分地基于确定处于拥塞状态的多个资源的数量来确定阈值。 还公开了其他实施例。

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