公开(公告)号：US07127640B2

公开(公告)日：2006-10-24

申请号：US10611467

申请日：2003-06-30

Applicant: Ishwardutt Parulkar ,  Chitresh C. Narasimhaiah

Inventor： Ishwardutt Parulkar ,  Chitresh C. Narasimhaiah

IPC: G06F11/00

CPC classification number: G11C29/16 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: A system for on-chip testing of embedded memories using Address Space Identifier (ASI) bus in Scalable Processor ARChitecture (SPARC) microprocessors. An integrated circuit includes a plurality of memory arrays, Address Space Identifier (ASI) bus interface logic connected by an ASI bus to the plurality of memory arrays, and a memory control unit and a memory built-in self-test (MBIST) engine connected to the ASI bus interface logic. Rather than direct access, the MBIST engine utilizes the ASI bus interface logic and the ASI bus to perform memory testing. The MBIST engine, programmed with memory array parameters, includes a programmable state machine controller to which is connected a programmable data generator, a programmable address generator, and a programmable comparator. The data generator provides data as appropriate. The address generator provides addresses as appropriate. The comparator provides test results information for the particular test situation. The MBIST engine generates a test status output.

Abstract translation: 在可扩展处理器ARChitecture（SPARC）微处理器中使用地址空间标识符（ASI）总线对嵌入式存储器进行片上测试的系统。 集成电路包括多个存储器阵列，通过ASI总线连接到多个存储器阵列的地址空间标识符（ASI）总线接口逻辑，以及连接到存储器控制单元和存储器内置自检（MBIST）引擎 到ASI总线接口逻辑。 MBIST引擎不是直接访问，而是使用ASI总线接口逻辑和ASI总线进行内存测试。 使用存储器阵列参数编程的MBIST引擎包括可编程状态机控制器，其连接有可编程数据发生器，可编程地址发生器和可编程比较器。 数据发生器根据需要提供数据。 地址生成器根据需要提供地址。 比较器提供特定测试情况的​​测试结果信息。 MBIST引擎生成测试状态输出。

公开(公告)号：US06578168B1

公开(公告)日：2003-06-10

申请号：US09616825

申请日：2000-07-14

Applicant: Ishwardutt Parulkar ,  Sridhar Narayanan ,  Gajendra P. Singh ,  Jaya Prakash Samala

Inventor： Ishwardutt Parulkar ,  Sridhar Narayanan ,  Gajendra P. Singh ,  Jaya Prakash Samala

IPC: G01R3128

CPC classification number: G06F11/267 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318552

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract translation: 一种边界扫描单元设计，其将多路复用器放置在功能线路上的功能翻转之前，减少了关键路径中的多路复用器延迟。 这优化了多路复用器和功能触发器方向，从而显着减少了从功能触发器输出到引脚或CPU内部（时钟到q延迟）所需的时间。 为了确保边界扫描模式正常工作，当边界扫描单元处于边界扫描模式时，功能触发器可被设计为充当缓冲器，即变得透明。

公开(公告)号：US06567944B1

公开(公告)日：2003-05-20

申请号：US09616826

申请日：2000-07-14

Applicant: Gajendra P. Singh ,  Jaya Prakash Samala ,  Sridhar Narayanan ,  Ishwardutt Parulkar

Inventor： Gajendra P. Singh ,  Jaya Prakash Samala ,  Sridhar Narayanan ,  Ishwardutt Parulkar

IPC: G01R3128

CPC classification number: G01R31/318536 ,  G01R31/318541 ,  G01R31/318552 ,  G06F11/27

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract translation: 一种边界扫描单元设计，其将多路复用器放置在功能线路上的功能翻转之前，减少了关键路径中的多路复用器延迟。 这优化了多路复用器和功能触发器方向，从而显着减少了从功能触发器输出到引脚或CPU内部（时钟到q延迟）所需的时间。 为了确保边界扫描模式正常工作，当边界扫描单元处于边界扫描模式时，功能触发器可被设计为充当缓冲器，即变得透明。

公开(公告)号：US20170034797A1

公开(公告)日：2017-02-02

申请号：US14860181

申请日：2015-09-21

Applicant: Ishwardutt Parulkar ,  Karuppusamy Marappagounder ,  Manoj I. Somakumaran

Inventor： Ishwardutt Parulkar ,  Karuppusamy Marappagounder ,  Manoj I. Somakumaran

IPC: H04W56/00

CPC classification number: H04W56/001

Abstract: In one embodiment, a timing slave packet switching device receives a received primary reference clock signal. The timing slave packet switching device communicates a first plurality of packet network synchronization packets over a packet switching network with a remote primary reference clock source and derives an over-network clock based on the first plurality of packet network synchronization packets. A phase offset between the phase of the over-network clock and the phase of the received primary reference clock signal is determined and typically stored in non-volatile storage. Subsequent to said determining the phase offset, the timing slave packet switching device communicates a second plurality of packet network synchronization packets over the packet switching network with the remote primary reference clock source and adjusts the phase of a clock derived from the second plurality of packet network synchronization packets based on the phase offset.

Abstract translation: 在一个实施例中，定时从分组交换设备接收接收的主参考时钟信号。 定时从分组交换设备通过分组交换网络与远程主参考时钟源通信第一多个分组网络同步分组，并且基于第一多个分组网络同步分组导出超网络时钟。 确定过网络时钟的相位与接收的主参考时钟信号的相位之间的相位偏移，并且通常将其存储在非易失性存储器中。 在所述确定相位偏移之后，定时从分组交换设备通过分组交换网络与远程主参考时钟源通信第二多个分组网络同步分组，并且调整从第二多个分组网络导出的时钟的相位 基于相位偏移的同步数据包。

公开(公告)号：US07757133B1

公开(公告)日：2010-07-13

申请号：US11773554

申请日：2007-07-05

Applicant: Ishwardutt Parulkar

Inventor： Ishwardutt Parulkar

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/20 ,  G11C29/16 ,  G11C2029/3602

Abstract: An integrated circuit (IC) having a memory built-in self-test (MBIST) controller. The IC includes an MBIST controller and a plurality of memory arrays. One or more the memory arrays has a different physical organization with respect to other ones of the memory arrays. The MBIST controller is configured to generate a logical address of a memory under test. The MBIST controller is further configured to permute the bits to produce a physical address. The user programmed permutation enables a simple address incrementer to create an address sequence that traverses the physical organization of the memory in accordance with the type of desired test.

Abstract translation: 具有存储器内置自检（MBIST）控制器的集成电路（IC）。 IC包括MBIST控制器和多个存储器阵列。 一个或多个存储器阵列相对于其他存储器阵列具有不同的物理组织。 MBIST控制器被配置为生成被测存储器的逻辑地址。 MBIST控制器被进一步配置为置位以产生物理地址。 用户编程的置换使得简单的地址增量器可以根据所需测试的类型创建遍历存储器的物理组织的地址序列。

公开(公告)号：US07650543B2

公开(公告)日：2010-01-19

申请号：US11582798

申请日：2006-10-18

Applicant: Ishwardutt Parulkar

Inventor： Ishwardutt Parulkar

IPC: G01R31/28

CPC classification number: G01R31/31905 ,  G01R31/31926 ,  G01R31/31937

Abstract: A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input having an interconnect coupled thereto. In a normal mode of operation, the first receiver is configured to receive data transmitted plesiochronously over the interconnect and to convey the data, via the first data path, to the core logic unit. The integrated circuit also includes a second data path coupled between the core logic unit and the interconnect. In a test mode, the core logic unit is configured to receive test stimulus data conveyed synchronously over the second data path, wherein the test stimulus data is received by the IC from the ATE via the interconnect.

Abstract translation: 一种用于经由同步互连将测试激励数据从ATE系统传送到集成电路（IC）的方法和装置。 IC包括核心逻辑单元和通过第一数据路径耦合到核心逻辑单元的第一接收器。 第一接收机包括具有耦合到其的互连的输入。 在正常操作模式中，第一接收器被配置为接收通过互连线以多个方式发送的数据，并且经由第一数据路径将数据传送到核心逻辑单元。 集成电路还包括耦合在核心逻辑单元和互连之间的第二数据路径。 在测试模式中，核心逻辑单元被配置为接收通过第二数据路径同步传送的测试激励数据，其中测试激励数据由IC经由互连从ATE接收。

公开(公告)号：US20080115020A1

公开(公告)日：2008-05-15

申请号：US11582798

申请日：2006-10-18

Applicant: Ishwardutt Parulkar

Inventor： Ishwardutt Parulkar

IPC: G01R31/28

CPC classification number: G01R31/31905 ,  G01R31/31926 ,  G01R31/31937

Abstract: A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input having an interconnect coupled thereto. In a normal mode of operation, the first receiver is configured to receive data transmitted plesiochronously over the interconnect and to convey the data, via the first data path, to the core logic unit. The integrated circuit also includes a second data path coupled between the core logic unit and the interconnect. In a test mode, the core logic unit is configured to receive test stimulus data conveyed synchronously over the second data path, wherein the test stimulus data is received by the IC from the ATE via the interconnect.

Abstract translation: 一种用于经由同步互连将测试激励数据从ATE系统传送到集成电路（IC）的方法和装置。 IC包括核心逻辑单元和通过第一数据路径耦合到核心逻辑单元的第一接收器。 第一接收机包括具有耦合到其的互连的输入。 在正常操作模式中，第一接收器被配置为接收通过互连线以多个方式发送的数据，并且经由第一数据路径将数据传送到核心逻辑单元。 集成电路还包括耦合在核心逻辑单元和互连之间的第二数据路径。 在测试模式中，核心逻辑单元被配置为接收通过第二数据路径同步传送的测试激励数据，其中测试激励数据由IC经由互连从ATE接收。

公开(公告)号：US06658632B1

公开(公告)日：2003-12-02

申请号：US09594656

申请日：2000-06-15

Applicant: Ishwardutt Parulkar ,  Sridhar Narayanan

Inventor： Ishwardutt Parulkar ,  Sridhar Narayanan

IPC: G06F1750

CPC classification number: G01R31/318594 ,  G01R31/318541 ,  G01R31/318572

Abstract: An electrical circuit includes a flip-flop, a first multiplexer, a second flip-flop, a third flip-flop, and output storage element including a second multiplexer and a fourth flip-flop. The first flip-flop, clocked functional clock signal, receives a functional signal. The first multiplexer receives the output of the first flip-flop and a test mode shift-in signal, and outputs one of them based on the state of a select input. The second flip-flop, clocked by a test clock signal, receives the output of the first multiplexer. The third flip-flop, clocked by a second test clock signal, receives the output of the second flip-flop. The second multiplexer receives the functional signal and the output of the third flip-flop, and outputs one of them based on a mode select input signal. The fourth flip-flop, clocked by a pulse-controlled functional clock signal, receives the output of the second multiplexer.

Abstract translation: 电路包括触发器，第一多路复用器，第二触发器，第三触发器和包括第二多路复用器和第四触发器的输出存储元件。 第一个触发器，时钟功能时钟信号，接收功能信号。 第一多路复用器接收第一触发器的输出和测试模式移位信号，并且基于选择输入的状态输出其中之一。 由测试时钟信号计时的第二触发器接收第一多路复用器的输出。 由第二测试时钟信号计时的第三触发器接收第二触发器的输出。 第二多路复用器接收功能信号和第三触发器的输出，并根据模式选择输入信号输出它们之一。 由脉冲控制功能时钟信号计时的第四触发器接收第二多路复用器的输出。

公开(公告)号：US07890826B2

公开(公告)日：2011-02-15

申请号：US11636748

申请日：2006-12-11

Applicant: Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

Inventor： Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

IPC: G01R31/28 ,  H03K19/00

CPC classification number: G01R31/318544 ,  G01R31/318594

Abstract: A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch data responsive to an indication from the control circuit, and a combinational logic circuit coupled to receive data from an output of the latch circuit. Each of the latch circuits is scannable. The latch circuits of the first and second pluralities of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the data pipeline. The data pipeline further includes a control scan chain configured to load control data for operating the control circuits during testing of the data pipeline. Testing of the data pipeline can include independent testing of the control portion or the data portion.

Abstract translation: 一种用于异步管道测试的方法和装置。 异步数据流水线包括交替序列中的第一和第二多个流水线级。 每个流水线级包括控制电路，锁存电路，被配置为响应于来自控制电路的指示来锁存数据;以及组合逻辑电路，被耦合以从锁存电路的输出接收数据。 每个锁存电路都是可扫描的。 第一和第二多个流水线级的锁存电路形成数据扫描链，其配置为在测试数据管线期间将测试数据加载到组合逻辑电路中。 数据流水线还包括控制扫描链，其被配置为在测试数据流水线期间加载用于操作控制电路的控制数据。 数据管线的测试可以包括控制部分或数据部分的独立测试。

公开(公告)号：US07779316B2

公开(公告)日：2010-08-17

申请号：US11950578

申请日：2007-12-05

Applicant: Ishwardutt Parulkar ,  Gaurav H. Agarwal ,  Krishna B. Rajan ,  Paul J. Dickinson

Inventor： Ishwardutt Parulkar ,  Gaurav H. Agarwal ,  Krishna B. Rajan ,  Paul J. Dickinson

IPC: G11C29/00

CPC classification number: G06F11/267 ,  G01R31/318533

Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

Abstract translation: 用于以功能（操作）速度测试芯片的方法和系统。 芯片可以包括具有布置成逻辑功能元件的数字触发器和存储器阵列的集成电路。 可以包括额外的触发器以输出到一个或多个其他触发器，以便以功能速度向触发器提供输入，使得接收触发器在下一个功能时钟脉冲下根据所接收的输入以功能速度执行，以便于 以功能速度测试芯片。