公开(公告)号：US10043303B2

公开(公告)日：2018-08-07

申请号：US15086033

申请日：2016-03-30

Applicant: Intel IP Corporation

Inventor： Ingo Wald ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/50 ,  G06T15/06 ,  G06T15/00

Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210342968A1

公开(公告)日：2021-11-04

申请号：US17322146

申请日：2021-05-17

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T1/20 ,  G06F13/16 ,  G06F13/00 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

公开(公告)号：US11443405B2

公开(公告)日：2022-09-13

申请号：US17322146

申请日：2021-05-17

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06F13/16 ,  G06F13/00 ,  G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

公开(公告)号：US11010858B2

公开(公告)日：2021-05-18

申请号：US16255721

申请日：2019-01-23

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06F13/16 ,  G06F13/00 ,  G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

公开(公告)号：US20180308273A1

公开(公告)日：2018-10-25

申请号：US16024042

申请日：2018-06-29

Applicant: Intel IP Corporation

Inventor： Ingo Wald ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005

Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170287202A1

公开(公告)日：2017-10-05

申请号：US15086033

申请日：2016-03-30

Applicant: Intel IP Corporation

Inventor： Ingo Wald ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06

Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US11798123B2

公开(公告)日：2023-10-24

申请号：US17895644

申请日：2022-08-25

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06F13/16 ,  G06T1/20 ,  G06T1/60 ,  G06F13/00 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F9/505 ,  G06F13/00 ,  G06F13/1652 ,  G06F13/1657 ,  G06T1/60 ,  G06T2200/28 ,  Y02D10/00

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

公开(公告)号：US20230119093A1

公开(公告)日：2023-04-20

申请号：US17895644

申请日：2022-08-25

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T1/20 ,  G06F13/16 ,  G06F13/00 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

公开(公告)号：US10553010B2

公开(公告)日：2020-02-04

申请号：US15477035

申请日：2017-04-01

Applicant: Intel IP Corporation

Inventor： Sven Woop ,  Attila Afra ,  Carsten Benthin ,  Ingo Wald ,  Johannes Guenther

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/20

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

公开(公告)号：US10229470B2

公开(公告)日：2019-03-12

申请号：US15229550

申请日：2016-08-05

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06F13/00 ,  G06T1/20 ,  G06T1/60 ,  G06F13/16

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.