公开(公告)号：US10699980B2

公开(公告)日：2020-06-30

申请号：US15938741

申请日：2018-03-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Bernd Waidhas ,  Thomas Ort ,  Thomas Wagner

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US10403580B2

公开(公告)日：2019-09-03

申请号：US15858103

申请日：2017-12-29

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

公开(公告)号：US10720393B2

公开(公告)日：2020-07-21

申请号：US16458675

申请日：2019-07-01

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

公开(公告)号：US20200251396A1

公开(公告)日：2020-08-06

申请号：US16855418

申请日：2020-04-22

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20190206799A1

公开(公告)日：2019-07-04

申请号：US15857189

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/145 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

公开(公告)号：US20200303274A1

公开(公告)日：2020-09-24

申请号：US16894434

申请日：2020-06-05

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Bernd Waidhas ,  Thomas Ort ,  Thomas Wagner

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20190206777A1

公开(公告)日：2019-07-04

申请号：US15857207

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Lizabeth Keser ,  Bernd Waidhas ,  Georg Seidmann

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H05K3/4007 ,  H05K2201/095 ,  H05K2201/10378

Abstract: An interposer for an electronic package including at least one angled via. The interposer can include a dielectric layer including a first surface and a second surface. The dielectric layer can include a normal axis perpendicular with the first or second surface. In an example, an angled via can include a first end located along the first surface and a second end located along the second surface. A longitudinal axis of the angled via can be extended between the first end and the second end. The longitudinal axis is disposed at an angle from the normal axis to form an angled via.

公开(公告)号：US10665522B2

公开(公告)日：2020-05-26

申请号：US15853173

申请日：2017-12-22

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US10546817B2

公开(公告)日：2020-01-28

申请号：US15857189

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/16

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

公开(公告)号：US20190393154A1

公开(公告)日：2019-12-26

申请号：US16458675

申请日：2019-07-01

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.