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1.发明授权Soft dark bit masking with integrated load modulation and burn-in induced destabilization for physically unclonable function keys 有权具有集成负载调制功能的软暗位屏蔽，并为物理不可克隆功能键老化引起不稳定公开(公告)号：US09276583B1
公开(公告)日：2016-03-01
申请号：US14748591
申请日：2015-06-24
Applicant: Intel Corporation
Inventor： Sudhir K Satpathy , Sanu K Mathew
IPC: H03K19/00 , H03K19/177 , G06F11/07
CPC classification number: H03K19/17768 , G06F11/0745
Abstract: Embodiments of an invention for soft dark bit masking are disclosed. In one embodiment, an apparatus includes a basic physically unclonable function (PUF) cell, a load, and a masking circuit. The load is selectively connectable to the basic PUF cell to determine whether the basic PUF cell is unstable. The masking circuit is to mask the output of the basic PUF cell if the basic PUF cell is determined to be unstable. Embodiments of the invention also include mechanisms to reinforce the stability of stable cells, while further destabilizing unstable cells.
Abstract translation: 公开了用于软暗位掩蔽的本发明的实施例。 在一个实施例中，一种装置包括基本的物理不可克隆功能（PUF）单元，负载和屏蔽电路。 负载可选择性地连接到基本PUF单元，以确定基本PUF单元是否不稳定。 如果基本PUF单元被确定为不稳定，则屏蔽电路用于屏蔽基本PUF单元的输出。 本发明的实施方案还包括增强稳定细胞的稳定性的机制，同时进一步使稳定的细胞不稳定。
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公开(公告)号：US10797858B2
公开(公告)日：2020-10-06
申请号：US15887290
申请日：2018-02-02
Applicant: Intel Corporation
Inventor： Vikram B Suresh , Sanu K. Mathew , Sudhir K Satpathy , Vinodh Gopal
Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X−1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.
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公开(公告)号：US10395035B2
公开(公告)日：2019-08-27
申请号：US15277195
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , Sudhir K Satpathy , Vikram B Suresh , Patrick Koeberl
Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.
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