公开(公告)号：US11953826B2

公开(公告)日：2024-04-09

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

CPC classification number: G03F7/0035 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/027 ,  H01L21/0274 ,  H01L21/768 ,  H01L21/76802

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US11251072B2

公开(公告)日：2022-02-15

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L. Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11137681B2

公开(公告)日：2021-10-05

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US10553532B2

公开(公告)日：2020-02-04

申请号：US15529484

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Richard E. Schenker ,  Manish Chandhok ,  Robert L. Bristol ,  Mauro J. Kobrinsky ,  Kevin Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/532

Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

公开(公告)号：US10269622B2

公开(公告)日：2019-04-23

申请号：US15529479

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Michael J. Leeson ,  Todd R. Younkin ,  Eungnak Han ,  Robert L. Bristol

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G03F7/00 ,  G03F7/16 ,  H01L21/027

Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.

公开(公告)号：US09793163B2

公开(公告)日：2017-10-17

申请号：US14912036

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Florian Gstrein ,  Richard E. Schenker ,  Paul A. Nyhus ,  Charles H. Wallace ,  Hui Jae Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US11854787B2

公开(公告)日：2023-12-26

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20210375745A1

公开(公告)日：2021-12-02

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: H01L23/528 ,  H01L23/522

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US11069609B2

公开(公告)日：2021-07-20

申请号：US16647691

申请日：2017-11-03

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Jasmeet S. Chawla ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young ,  Robert L. Bristol

IPC: H01L23/522 ,  H01F10/32 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/02

Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.