公开(公告)号：US09627358B2

公开(公告)日：2017-04-18

申请号：US14368774

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L21/50 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L21/565 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/32225

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US20210005577A1

公开(公告)日：2021-01-07

申请号：US16852747

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US09589934B2

公开(公告)日：2017-03-07

申请号：US14368774

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L21/50 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US20150359100A1

公开(公告)日：2015-12-10

申请号：US14432195

申请日：2014-04-30

Applicant: INTEL CORPORATION

Inventor： Junfeng Zhao ,  Saeed S. Shojaie ,  Cheng Yang

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/36 ,  H05K1/14

CPC classification number: H05K1/181 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/14 ,  H05K3/303 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0415 ,  Y10T29/49128 ,  Y10T29/49131

Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了集成电路（IC）组件和相关技术的实施例。 例如，在一些实施例中，IC组件可以包括具有第一面和相对的第二面的第一印刷电路板（PCB） 电连接到第一PCB的第一面的模具; 第二PCB，其具有第一面和相对的第二面，其中所述第二PCB的所述第二面经由一个或多个焊点而耦合到所述第一PCB的所述第一面; 和模塑料。 模塑料可以与第一PCB的第一面和第二PCB的第二面接触。 可以公开和/或要求保护其他实施例。

公开(公告)号：US12033983B2

公开(公告)日：2024-07-09

申请号：US18196905

申请日：2023-05-12

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L25/065 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L21/50 ,  H01L21/565 ,  H01L23/49816 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US20210327853A1

公开(公告)日：2021-10-21

申请号：US17246982

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US20190189585A1

公开(公告)日：2019-06-20

申请号：US16282824

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Junfeng Zhao ,  Cheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/45 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012

Abstract: Some forms relate to an electronic assembly that includes a die that includes an upper surface and a conductive column extending from the upper surface such that the conductive column is not surrounded by any material other than where the conductive column engages the die. Other forms relate to an electronic package that includes a stack of electronic assemblies where each electronic assembly includes a die that having an upper surface and a plurality of conductive columns extending from the upper surface such that each conductive column is not surrounded by any material other than where the conductive column engages the die, and wherein the stack of electronic assemblies is arranged in an overlapping configuration such the plurality of conductive columns on each electronic assembly are not covered by another electronic assembly.

公开(公告)号：US10256208B2

公开(公告)日：2019-04-09

申请号：US15509416

申请日：2014-10-03

Applicant: Intel Corporation

Inventor： Junfeng Zhao ,  Cheng Yang

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

Abstract: Some forms relate to an electronic assembly (10) that includes a die (11) that includes an upper surface (12) and a conductive column (13) extending from the upper surface (12) such that the conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11). Other forms relate to an electronic package (19) that includes a stack (20) of electronic assemblies (10) where each electronic assembly (10) includes a die (11) that having an upper surface (12) and a plurality of conductive columns (13) extending from the upper surface (12) such that each conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11), and wherein the stack (20) of electronic assemblies (10) is arranged in an overlapping configuration such the plurality of conductive columns (13) on each electronic assembly (10) are not covered by another electronic assembly (10).

公开(公告)号：US09936582B2

公开(公告)日：2018-04-03

申请号：US14432195

申请日：2014-04-30

Applicant: INTEL CORPORATION

Inventor： Junfeng Zhao ,  Saeed S. Shojaie ,  Cheng Yang

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H01L23/48 ,  H01L25/00 ,  H05K3/30 ,  H01L25/065 ,  H01L25/16

CPC classification number: H05K1/181 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/14 ,  H05K3/303 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0415 ,  Y10T29/49128 ,  Y10T29/49131

Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20230282619A1

公开(公告)日：2023-09-07

申请号：US18196905

申请日：2023-05-12

Applicant: Intel Corporation

Inventor： Junfeng Zhao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L2225/06544 ,  H01L21/565

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.