公开(公告)号：US11791380B2

公开(公告)日：2023-10-17

申请号：US16713670

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Walid M. Hafez ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ting Chang ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Nidhi Nidhi

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  B82Y40/00 ,  B82Y10/00

CPC classification number: H01L29/0669 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/785 ,  B82Y10/00 ,  B82Y40/00

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

公开(公告)号：US11094782B1

公开(公告)日：2021-08-17

申请号：US16795081

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US12249622B2

公开(公告)日：2025-03-11

申请号：US16713684

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Ting Chang ,  Walid M. Hafez ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Nidhi Nidhi

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y40/00

Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.

公开(公告)号：US11996403B2

公开(公告)日：2024-05-28

申请号：US16713656

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/66136

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

公开(公告)号：US11437483B2

公开(公告)日：2022-09-06

申请号：US16810156

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US12040395B2

公开(公告)日：2024-07-16

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US11862703B2

公开(公告)日：2024-01-02

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11581404B2

公开(公告)日：2023-02-14

申请号：US17308900

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/285

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.