公开(公告)号：US20160043021A1

公开(公告)日：2016-02-11

申请号：US14919653

申请日：2015-10-21

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H02M3/158

CPC classification number: H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Abstract translation: 公开了一种双功率转换器封装。 该封装包括引线框架，其具有被配置为支撑第一控制FET的漏极的第一控制FET栅极和被配置为支持第二控制FET的漏极的第二控制FET栅极。 所述引线框架还包括配置成支撑第一同步FET源和第二同步FET源的同步FET焊盘，以及配置成接收每个控制FET和每个同步FET的控制信号的第一多个触点 从引线框架外部的驱动器集成电路（IC）。 引线框架还可以包括第一和第二开关节点，其被配置用于经由第一夹子电连接到第一控制FET和第一同步FET，并且分别经由第二夹子连接到第二控制FET和第二同步FET。

公开(公告)号：US10074620B2

公开(公告)日：2018-09-11

申请号：US15013858

申请日：2016-02-02

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Darryl Galipeau ,  Dan Clavette

IPC: H01L23/64 ,  H01L23/49 ,  H01L23/31 ,  H01L23/495 ,  H01F17/00 ,  H02M3/158 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01F17/0033 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H02M3/158 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/00 ,  H01L2924/206

Abstract: A semiconductor package includes a semiconductor die having a control transistor and a sync transistor, an integrated output inductor having a winding around a core, and coupled to the semiconductor die, where the winding includes a plurality of top conductive clips connected to a plurality of bottom conductive clips. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of top conductive clips and the plurality of bottom conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

公开(公告)号：US20170063250A1

公开(公告)日：2017-03-02

申请号：US15299655

申请日：2016-10-21

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H02M7/00 ,  H01L21/56 ,  H01L29/16 ,  H01L29/78 ,  H02M7/217 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L49/02 ,  H01L21/48 ,  H01L29/20

CPC classification number: H02M7/003 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L25/16 ,  H01L28/10 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/7801 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M3/158 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括包括部分蚀刻的段的第一图案化导电载体。 半导体封装还包括具有附接到第一图案化导电载体的第一部分蚀刻段的控制漏极的控制FET。 此外，半导体封装包括具有同步源的同步FET和连接到第一图案化导电载体的相应的第二和第三部分蚀刻段的同步栅极。 半导体封装还包括第二图案化导电载体，其具有位于控制FET的控制源上方以及同步FET的同步漏极之上的开关节点段，以及耦合在开关节点段和输出段之间的电感器 第二图案化导电载体。

公开(公告)号：US20160286656A1

公开(公告)日：2016-09-29

申请号：US15013858

申请日：2016-02-02

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Darryl Galipeau ,  Dan Clavette

IPC: H05K1/18

CPC classification number: H01L23/645 ,  H01F17/0033 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H02M3/158 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor die having a control transistor and a sync transistor, an integrated output inductor having a winding around a core, and coupled to the semiconductor die, where the winding includes a plurality of top conductive clips connected to a plurality of bottom conductive clips. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of top conductive clips and the plurality of bottom conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Abstract translation: 半导体封装包括具有控制晶体管和同步晶体管的半导体管芯，集成的输出电感器，其具有围绕芯的绕组并且耦合到半导体管芯，其中所述绕组包括多个顶部导电夹子，其连接到多个底部 导电夹。 控制晶体管和同步晶体管被配置为半桥。 集成输出电感器耦合到半桥的开关节点。 多个顶部导电夹子和多个底部导电夹子中的至少一个包括部分蚀刻部分和非蚀刻部分。 半导体管芯通过管芯附着材料附接到集成输出电感器。 半导体管芯和集成输出电感器被封装在模塑料中。

公开(公告)号：US09762137B2

公开(公告)日：2017-09-12

申请号：US15299655

申请日：2016-10-21

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L21/44 ,  H02M7/00 ,  H01L23/495 ,  H01L23/66 ,  H01L49/02 ,  H01L29/778 ,  H02M3/158 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H02M7/217

CPC classification number: H02M7/003 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L25/16 ,  H01L28/10 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/7801 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M3/158 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

公开(公告)号：US09589872B2

公开(公告)日：2017-03-07

申请号：US13759734

申请日：2013-02-05

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/495 ,  H01L25/16

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L25/16 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Abstract translation: 公开了一种集成的双电源转换器封装。 该封装包括引线框架，其具有被配置为支撑第一控制FET的漏极的第一控制FET栅极和被配置为支持第二控制FET的漏极的第二控制FET栅极。 引线框架还包括配置成支持第一同步FET源和第二同步FET源的同步FET焊盘，驱动器集成电路（IC）焊盘被配置为支持用于控制每个控制FET的驱动器IC，以及 每个同步FET。 引线框架还可以包括第一和第二开关节点，其被配置用于经由第一夹子电连接到第一控制FET和第一同步FET，并且分别经由第二夹子连接到第二控制FET和第二同步FET。

公开(公告)号：US09812383B2

公开(公告)日：2017-11-07

申请号：US14920424

申请日：2015-10-22

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/00 ,  H01L25/07 ,  H02M3/158

CPC classification number: H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

公开(公告)号：US09799586B2

公开(公告)日：2017-10-24

申请号：US14919653

申请日：2015-10-21

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/00 ,  H01L25/07 ,  H02M3/158

CPC classification number: H01L23/49562 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H02M3/158 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/84

Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

公开(公告)号：US09515014B2

公开(公告)日：2016-12-06

申请号：US14855665

申请日：2015-09-16

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/66 ,  H01L49/02 ,  H01L29/778 ,  H02M3/158

CPC classification number: H02M7/003 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L25/16 ,  H01L28/10 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/7801 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M3/158 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括包括部分蚀刻的段的第一图案化导电载体。 半导体封装还包括具有附接到第一图案化导电载体的第一部分蚀刻段的控制漏极的控制FET。 此外，半导体封装包括具有同步源的同步FET和连接到第一图案化导电载体的相应的第二和第三部分蚀刻段的同步栅极。 半导体封装还包括第二图案化导电载体，其具有位于控制FET的控制源上方并且在同步FET的同步漏极之上的开关节点段，以及耦合在开关节点段和输出段之间的电感器 第二图案化导电载体。

公开(公告)号：US09502338B2

公开(公告)日：2016-11-22

申请号：US14795527

申请日：2015-07-09

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho ,  Dan Clavette

IPC: H01L23/495 ,  H01L21/52 ,  H01L23/00 ,  H01L23/433 ,  H01L23/367 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L23/49575 ,  H01L21/52 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括包括部分蚀刻的段的图案化导电载体。 半导体封装还包括具有附着到图案化导电载体的第一部分蚀刻段的控制漏极的控制FET。 此外，半导体封装包括具有同步源和同步栅极的同步FET，其连接到图案化导电载体的相应的第二和第三部分蚀刻段。 半导体封装还包括位于控制FET的控制源上方并且在同步FET的同步漏极之上的散热导电板，以将控制源和同步漏极耦合到图案化导电载体的开关节点段。