公开(公告)号：US12260316B2

公开(公告)日：2025-03-25

申请号：US15709699

申请日：2017-09-20

Applicant: International Business Machines Corporation

Inventor： Pallab Datta ,  Myron D. Flickner ,  Dharmendra S. Modha

IPC: G06N3/063 ,  G06N3/049

Abstract: A neural network may include a set of components. The set of components may have timing requirements and a topological order. The relative timing of each component may be computed and the dependencies of the set of components may be enumerated. Mutable components within the set of components may be identified, and the relative timing of the mutable components may be adjusted to satisfy the timing requirements of each component in the set of components.

公开(公告)号：US12182687B2

公开(公告)日：2024-12-31

申请号：US16157852

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John V. Arthur ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Pallab Datta ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  Dharmendra S. Modha ,  Steven K. Esser ,  Brian Taba ,  Jennifer Klamo

IPC: G06N3/063 ,  G06N3/04

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

公开(公告)号：US12056598B2

公开(公告)日：2024-08-06

申请号：US18046301

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew S. Cassidy ,  Rathinakumar Appuswamy ,  John V. Arthur ,  Pallab Datta ,  Steven K. Esser ,  Myron D. Flickner ,  Jennifer Klamo ,  Dharmendra S. Modha ,  Hartmut Penner ,  Jun Sawada ,  Brian Taba

IPC: G06N3/063 ,  G06N3/048 ,  G06N3/08 ,  G06N5/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/048 ,  G06N3/08 ,  G06N5/04 ,  G11C11/54

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

公开(公告)号：US11232345B2

公开(公告)日：2022-01-25

申请号：US15917403

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/54 ,  G11C13/00 ,  G06N3/04 ,  G06N3/08

Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

公开(公告)号：US11200496B2

公开(公告)日：2021-12-14

申请号：US15792155

申请日：2017-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John V. Arthur ,  Pallab Datta ,  Steven K. Esser ,  Myron D. Flickner ,  Dharmendra S. Modha ,  Tapan K. Nayak

IPC: G06N3/08 ,  G06N3/06 ,  G06N3/04 ,  G06N3/063

Abstract: Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.

公开(公告)号：US11151444B2

公开(公告)日：2021-10-19

申请号：US15908403

申请日：2018-02-28

Applicant: International Business Machines Corporation

Inventor： Dharmendra S. Modha

IPC: G06N3/06 ,  G06N3/063 ,  G06N3/02 ,  G06N3/04 ,  G06N3/10

Abstract: Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.

公开(公告)号：US20210264279A1

公开(公告)日：2021-08-26

申请号：US16796397

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steve Esser ,  Jeffrey L. McKinstry ,  Deepika Bablani ,  Rathinakumar Appuswamy ,  Dharmendra S. Modha

IPC: G06N3/08 ,  G06F17/16 ,  G06N3/04

Abstract: Learned step size quantization in artificial neural network is provided. In various embodiments, a system comprises an artificial neural network and a computing node. The artificial neural network comprises: a quantizer having a configurable step size, the quantizer adapted to receive a plurality of input values and quantize the plurality of input values according to the configurable step size to produce a plurality of quantized input values, at least one matrix multiplier configured to receive the plurality of quantized input values from the quantizer and to apply a plurality of weights to the quantized input values to determine a plurality of output values having a first precision, and a multiplier configured to scale the output values to a second precision. The computing node is operatively coupled to the artificial neural network and is configured to: provide training input data to the artificial neural network, and optimize the configurable step size based on a gradient through the quantizer and the training input data.

公开(公告)号：US11049001B2

公开(公告)日：2021-06-29

申请号：US16049539

申请日：2018-07-30

Applicant: International Business Machines Corporation

Inventor： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC: G06N3/063

Abstract: The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.

公开(公告)号：US10929747B2

公开(公告)日：2021-02-23

申请号：US15950033

申请日：2018-04-10

Applicant: International Business Machines Corporation

Inventor： Rodrigo Alvarez-Icaza ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC: G06N3/063 ,  G06N3/04

Abstract: One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.

公开(公告)号：US10832121B2

公开(公告)日：2020-11-10

申请号：US16391092

申请日：2019-04-22

Applicant: International Business Machines Corporation

Inventor： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F17/16

Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.