-
公开(公告)号：US11283469B2
公开(公告)日：2022-03-22
申请号：US17103969
申请日：2020-11-25
Applicant: Infineon Technologies AG
Inventor： Wieland Fischer , Bernd Meyer
IPC: H03M13/15
Abstract: An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.
-
公开(公告)号：US10937469B2
公开(公告)日：2021-03-02
申请号：US16666425
申请日：2019-10-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Jan Otterstedt , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
IPC: G11C7/10 , G06F11/10 , G06F11/25 , G06F12/02 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/34 , H03M13/13 , G11C29/26
Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.
-
公开(公告)号：US10649931B2
公开(公告)日：2020-05-12
申请号：US16258710
申请日：2019-01-28
Applicant: Infineon Technologies AG
Inventor： Gerd Dirscherl , Benedikt Driessen , Gunther Fenzl , Franz Klug , Bernd Meyer , Steffen Sonnekalb
Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.
-
公开(公告)号：US20180158534A1
公开(公告)日：2018-06-07
申请号：US15831439
申请日：2017-12-05
Applicant: Infineon Technologies AG
Inventor： Jan OTTERSTEDT , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
CPC classification number: G11C29/34 , G06F11/1048 , G06F11/25 , G06F12/0246 , G11C7/1006 , G11C16/08 , G11C16/105 , G11C16/26 , G11C2029/2602 , H03M13/13
Abstract: In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, wherein each word portion is configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion comprising a plurality of overlay memory cells, wherein each of the plurality of overlay portions comprises an overlay word, wherein the memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, thereby providing, as an output of the read operation, a result of a logic operation performed on the data word and the overlay word.
-
公开(公告)号：US20180151244A1
公开(公告)日：2018-05-31
申请号：US15821871
申请日：2017-11-24
Applicant: Infineon Technologies AG
Inventor： Jan Otterstedt , Robin Boch , Gerd Dirscherl , Bernd Meyer , Christian Peters , Steffen Sonnekalb
CPC classification number: G11C29/025 , G11C7/06 , G11C29/12005 , G11C29/702 , G11C29/82 , G11C2029/1202 , G11C2029/4402
Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.
-
Patent Agency Ranking
公开(公告)号：US20140129837A1
公开(公告)日：2014-05-08
申请号：US14152227
申请日：2014-01-10
Applicant: Infineon Technologies AG
Inventor： Cheow Guan Lim , Stephan Schaecher , Wieland Fischer , Bernd Meyer
IPC: H04L29/06
CPC classification number: H04L63/08 , H04L9/3066 , H04L9/3231 , H04L9/3242 , H04L9/3271 , H04L63/0428 , H04L2209/88
Abstract: Embodiments relate to systems and methods for authenticating devices and securing data. In embodiments, a session key for securing data between two devices can be derived as a byproduct of a challenge-response protocol for authenticating one or both of the devices.
Abstract translation: 实施例涉及用于认证设备和保护数据的系统和方法。 在实施例中，用于保护两个设备之间的数据的会话密钥可以被导出为询问 - 响应协议的副产品，用于认证一个或两个设备。
-
公开(公告)号：US11086796B2
公开(公告)日：2021-08-10
申请号：US16422911
申请日：2019-05-24
Applicant: Infineon Technologies AG
Inventor： Berndt Gammel , Gerd Dirscherl , Bernd Meyer , Steffen Sonnekalb
Abstract: A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.
-
8.发明申请公开(公告)号：US20190243789A1
公开(公告)日：2019-08-08
申请号：US16258710
申请日：2019-01-28
Applicant: Infineon Technologies AG
Inventor： Gerd Dirscherl , Benedikt Driessen , Gunther Fenzl , Franz Klug , Bernd Meyer , Steffen Sonnekalb
IPC: G06F13/20
CPC classification number: G06F13/20 , G06F2213/40
Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.
-
公开(公告)号：US20150074422A1
公开(公告)日：2015-03-12
申请号：US14022313
申请日：2013-09-10
Applicant: Infineon Technologies AG
Inventor： Bernd Meyer
CPC classification number: G06F21/55 , G06F21/556 , G06F21/77 , H04L9/004 , H04L9/3066 , H04L9/32
Abstract: According to one embodiment, an electronic circuit is described comprising a processing circuit configured to perform a data processing including a plurality of successive operations, wherein in at least some of the plurality of operations, a predetermined input value is processed; a check value memory; a controller configured to check, for each operation of the data processing performed by the processing circuit, whether the predetermined input value is processed in the operation, and, if the predetermined input value is processed in the operation, combine the predetermined input value to the content of the check value memory and a detector configured to check, when the processing is complete, whether the content of the check value memory is equal to a predetermined value.
Abstract translation: 根据一个实施例，描述了一种电子电路，其包括被配置为执行包括多个连续操作的数据处理的处理电路，其中在所述多个操作中的至少一些操作中处理预定输入值; 检查值记忆; 控制器，被配置为对于由处理电路执行的数据处理的每个操作检查在操作中是否处理了预定输入值，并且如果在操作中处理了预定输入值，则将预定输入值与 检查值存储器的内容和被配置为在处理完成时检查检查值存储器的内容是否等于预定值的检测器。
-
公开(公告)号：US11476872B2
公开(公告)日：2022-10-18
申请号：US16504863
申请日：2019-07-08
Applicant: Infineon Technologies AG
Inventor： Florian Mendel , Bernd Meyer
Abstract: A method is proposed for copying a source array into a target array, wherein both the source array and the target array have at least two elements, wherein each element has a value, in which the elements of the source array are copied into the target array in the sequence of a random permutation, wherein, after a step of copying an element of the source array into the target array, the source array, the target array or the source array and the target array are rotated. A device is also indicated accordingly.
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.015 seconds)
