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    Digital-to-analog converter with controlled buffered inputs
    1.
    发明申请
    Digital-to-analog converter with controlled buffered inputs 有权
    具有受控缓冲输入的数模转换器

    公开(公告)号：US20070296619A1

    公开(公告)日：2007-12-27

    申请号：US11474175

    申请日：2006-06-23

    Applicant: Gavin Cosgrave

    Inventor： Gavin Cosgrave

    IPC: H03M1/66

    CPC classification number: H03M1/0612 ,  H03M1/662 ,  H03M1/687

    Abstract: A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.

    Abstract translation: 提供DAC电路，其实现缓冲DAC输入，其中缓冲器由差分放大器提供，其差分放大器的电源轨与DAC的输入相关。 以这种方式，可以使用放大器对电路进行缓冲，其开环增益规格可以放宽，而不影响DAC的线性性能。

    Digital-to-analog converter with controlled buffered inputs
    2.
    发明授权
    Digital-to-analog converter with controlled buffered inputs 有权
    具有受控缓冲输入的数模转换器

    公开(公告)号：US07425912B2

    公开(公告)日：2008-09-16

    申请号：US11474175

    申请日：2006-06-23

    Applicant: Gavin Cosgrave

    Inventor： Gavin Cosgrave

    IPC: H03M1/68

    CPC classification number: H03M1/0612 ,  H03M1/662 ,  H03M1/687

    Abstract: A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.

    Abstract translation: 提供DAC电路，其实现缓冲DAC输入，其中缓冲器由差分放大器提供，其差分放大器的电源轨与DAC的输入相关。 以这种方式，可以使用放大器对电路进行缓冲，其开环增益规格可以放宽，而不影响DAC的线性性能。

    Digital-to-analogue converter
    4.
    发明授权
    Digital-to-analogue converter 有权
    数模转换器

    公开(公告)号：US07956786B2

    公开(公告)日：2011-06-07

    申请号：US12609580

    申请日：2009-10-30

    Applicant: Gavin Cosgrave

    Inventor： Gavin Cosgrave

    IPC: H03M1/66

    CPC classification number: H03M1/682 ,  H03M1/765

    Abstract: An N-bit DAC comprises a main DAC circuit having main nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one MSB value, and a sub-DAC circuit having secondary nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one LSB. A main switch network couples the secondary nodes to a selected pair of main nodes as the MSB value of the digital input signal varies. A secondary switch network selectively couples one of secondary nodes to an output terminal for providing an analogue voltage output signal. The main nodes are coupled between main terminals, and a voltage reference is applied across input terminals. A first offset circuit and a first compensating circuit are selectively coupleable between the main DAC circuit and the input terminals for offsetting the main node analogue voltages downwardly.

    Abstract translation: N位DAC包括主DAC电路，其主节点在其上产生逐步增加值的步骤中的一个MSB值的逐步增加的值，以及具有逐次产生模拟电压的次级节点的子DAC电路 以一个LSB​​的值增加值。 当数字输入信号的MSB值变化时，主交换机网络将辅助节点耦合到所选择的主节点对。 次级开关网络将二级节点中的一个选择性地耦合到输出端以提供模拟电压输出信号。 主节点耦合在主终端之间，并且在输入端之间施加电压基准。 第一偏移电路和第一补偿电路在主DAC电路和输入端子之间选择性地耦合，用于向下偏移主节点模拟电压。

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