公开(公告)号：US10283501B2

公开(公告)日：2019-05-07

申请号：US15447200

申请日：2017-03-02

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L29/778 ,  H01L21/78 ,  H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US09589868B2

公开(公告)日：2017-03-07

申请号：US15064750

申请日：2016-03-09

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak ,  Ahmad Mizan

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L23/492 ,  H01L23/482

CPC classification number: H01L23/49503 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

Abstract translation: 公开了用于大面积的包括一个或多个横向GaN功率晶体管器件和系统的GaN管芯的封装解决方案。 包装组件包括包括横向GaN管芯和引线框架的插入件子组件。 GaN管芯使用凸点或柱互连，银烧结或其他低电感互连电连接到引线框架。 然后，在单个工艺步骤中制造GaN管芯到衬底的连接以及引线框架与衬底上的触点的电连接。 子组件可以安装在标准功率模块中，或者替代地安装在诸如印刷电路板的基板上。 对于高电流应用，子组件还包括用于散热的陶瓷衬底。 与传统的引线键合功率模块相比，该封装方案提供了具有较低电感和较高电流容量的互连，简化了制造，并且能够改进组件的热匹配。

公开(公告)号：US10249506B2

公开(公告)日：2019-04-02

申请号：US15712373

申请日：2017-09-22

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L21/30 ,  H01L21/78 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L23/58 ,  H01L23/31 ,  H01L23/00 ,  C01B21/06 ,  H05B33/08 ,  C01G15/00 ,  H01L29/20

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US09818692B2

公开(公告)日：2017-11-14

申请号：US15078023

申请日：2016-03-23

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Greg P. Klowak ,  Cameron McKnight-MacNeil

IPC: H01L23/528 ,  H01L21/66 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L23/373 ,  H01L29/20 ,  H01L29/06 ,  H01L23/36

CPC classification number: H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

公开(公告)号：US11776883B2

公开(公告)日：2023-10-03

申请号：US17728220

申请日：2022-04-25

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak

IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/18 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/04105 ,  H01L2224/82 ,  H01L2924/13091

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

公开(公告)号：US09818857B2

公开(公告)日：2017-11-14

申请号：US15032824

申请日：2014-10-28

Applicant: GaN Systems Inc.

Inventor： Greg P. Klowak ,  Cameron McKnight-Macneil ,  Howard Tweddle ,  Ahmad Mizan ,  Nigel Springett

IPC: H01L29/20 ,  H01L29/778 ,  H01L21/66 ,  H01L29/201 ,  H01L29/205 ,  H01L27/095 ,  H01L23/528 ,  H01L29/417 ,  H01L23/482 ,  H01L29/06 ,  H01L29/16 ,  H01L29/861 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

公开(公告)号：US09589869B2

公开(公告)日：2017-03-07

申请号：US15064955

申请日：2016-03-09

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak ,  Ahmad Mizan

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/492 ,  H01L23/482

CPC classification number: H01L23/49503 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的封装解决方案，包括封装组件的部件，半导体器件结构及其制造方法。 在封装组件中，包括一个或多个横向GaN功率晶体管的GaN管芯被夹在第一和第二引线框层之间，并且使用低电感互连互连，而无需引线接合。 为了散热，双引线框封装组件可以配置为正面或背面冷却。 优选的实施例有利于用于横向GaN器件的高电流/低电感互连的对准和配准，其中用于源极，漏极和栅极接触的接触区域或焊盘设置在GaN管芯的前侧。 通过消除引线键合，并且使用具有高导电和导热性的低电感互连，PQFN技术可以适用于封装包含一个或多个横向GaN功率晶体管的GaN晶体管。

公开(公告)号：USRE49603E1

公开(公告)日：2023-08-08

申请号：US16868632

申请日：2020-05-07

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02 ,  H01L29/778 ,  H01L21/78

CPC classification number: H01L27/088 ,  H01L21/3043 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/585 ,  H01L29/2003 ,  H01L29/778

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US10218346B1

公开(公告)日：2019-02-26

申请号：US15704458

申请日：2017-09-14

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Greg P. Klowak ,  Xiaodong Cui

IPC: H01L29/20 ,  H01L23/522 ,  H01L29/778 ,  H03K17/081 ,  H01L29/205 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L23/31

Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

公开(公告)号：US09692408B2

公开(公告)日：2017-06-27

申请号：US14654127

申请日：2013-12-12

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Greg P. Klowak

IPC: H03K3/00 ,  H03K17/687 ,  H01L25/18 ,  H01L23/495 ,  H01F19/08 ,  H01L23/64 ,  H01L23/00

CPC classification number: H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.