公开(公告)号：US10854284B1

公开(公告)日：2020-12-01

申请号：US16785141

申请日：2020-02-07

Applicant: GSI Technology, Inc.

Inventor： Patrick Chuang ,  Chao-Hung Chang ,  Lee-Lean Shu

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

公开(公告)号：US09196324B2

公开(公告)日：2015-11-24

申请号：US14170497

申请日：2014-01-31

Applicant: GSI Technology, Inc.

Inventor： Robert Haig ,  Patrick Chuang ,  Chih Tseng ,  Mu-Hsiang Huang

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/419 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G06F13/1615 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Abstract translation: 公开了用于增加静态随机存取存储器（SRAM）的性能的系统和方法。 这里的各种系统例如可以包括或涉及双管或多管多段SRAM，例如Quad-B2 SRAM。 在一个说明性实现中，提供了一种SRAM存储器件，其包括存储器阵列，该存储器阵列包括多个SRAM组以及与每个SRAM组相关联的独立和不同的管对，其中每对管可以提供对其相关联的SRAM的独立访问 银行。

公开(公告)号：US11194519B2

公开(公告)日：2021-12-07

申请号：US16713383

申请日：2019-12-13

Applicant: GSI TECHNOLOGY, INC.

Inventor： Bob Haig ,  Eli Ehrman ,  Dan Ilan ,  Patrick Chuang ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC: G11C11/419 ,  G06F3/06

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

公开(公告)号：US10943648B1

公开(公告)日：2021-03-09

申请号：US16785153

申请日：2020-02-07

Applicant: GSI Technology, Inc.

Inventor： Lee-Lean Shu ,  Patrick Chuang ,  Chao-Hung Chang

IPC: G11C11/00 ,  G11C11/419 ,  H03K19/0944 ,  G11C11/412

Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

公开(公告)号：US20180109248A1

公开(公告)日：2018-04-19

申请号：US15845578

申请日：2017-12-18

Applicant: GSI Technology, Inc.

Inventor： Yu-Chi Cheng ,  Patrick Chuang ,  Jae-Hyeong Kim

IPC: H03K5/15 ,  H03L7/081

Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

公开(公告)号：US09679631B2

公开(公告)日：2017-06-13

申请号：US14951160

申请日：2015-11-24

Applicant: GSI Technology, Inc.

Inventor： Robert Haig ,  Patrick Chuang ,  Chih Tseng ,  Mu-Hsiang Huang

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10 ,  G11C11/419 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G06F13/1615 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

公开(公告)号：US09613670B2

公开(公告)日：2017-04-04

申请号：US15068075

申请日：2016-03-11

Applicant: GSI TECHNOLOGY, INC.

Inventor： Patrick Chuang ,  Mu-Hsiang Huang ,  Lee-Lean Shu

IPC: G11C7/00 ,  G11C8/10 ,  G11C8/08 ,  G11C7/10 ,  G11C16/08 ,  G11C8/06

CPC classification number: G11C8/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C8/08 ,  G11C16/08

Abstract: Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer. When the first buffer draws a current from the power input, at least a portion of the current may be supplied by the capacitor.

公开(公告)号：US10891076B1

公开(公告)日：2021-01-12

申请号：US16152374

申请日：2018-10-04

Applicant: GSI Technology, Inc.

Inventor： Bob Haig ,  Eli Ehrman ,  Dan Ilan ,  Patrick Chuang ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC: G11C11/419 ,  G06F3/06

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

公开(公告)号：US09853633B1

公开(公告)日：2017-12-26

申请号：US15188907

申请日：2016-06-21

Applicant: GSI Technology, Inc.

Inventor： Yu-Chi Cheng ,  Patrick Chuang ,  Jae-Hyeong Kim

IPC: H03L7/06 ,  H03K5/15 ,  H03L7/081

CPC classification number: H03K5/1506 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/16

Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

公开(公告)号：US09318174B1

公开(公告)日：2016-04-19

申请号：US14207350

申请日：2014-03-12

Applicant: GSI TECHNOLOGY, INC.

Inventor： Patrick Chuang ,  Mu-Hsiang Huang ,  Lee-Lean Shu

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C8/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C8/08 ,  G11C16/08

Abstract: Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer. When the first buffer draws a current from the power input, at least a portion of the current may be supplied by the capacitor.

Abstract translation: 公开了存储器和存储器操作的系统和方法，例如提供包括用于存储器解码的本地地址驱动器电压源的电路。 在一个示例性实现中，说明性电路可以包括第一缓冲器和电容器。 第一缓冲器可以包括电源输入和接地输入。 电容器可以包括连接到第一缓冲器的电力输入端的第一端子和连接到第一缓冲器的接地输入端的第二端子。 当第一缓冲器从电源输入端吸取电流时，电流的至少一部分可由电容器提供。