公开(公告)号：US11437080B2

公开(公告)日：2022-09-06

申请号：US17092384

申请日：2020-11-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

公开(公告)号：US11923024B2

公开(公告)日：2024-03-05

申请号：US17655389

申请日：2022-03-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C29/00 ,  G06F1/06 ,  G11C29/12 ,  H03K3/037 ,  G11C11/417

CPC classification number: G11C29/12015 ,  G06F1/06 ,  H03K3/037 ,  G11C11/417

Abstract: Embodiments of the present disclosure provide a level-sensitive register unit, including: a data latch for receiving data; a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop; a first clock signal coupled to the data latch; and a second clock signal, wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.

公开(公告)号：US20220148633A1

公开(公告)日：2022-05-12

申请号：US17092384

申请日：2020-11-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

公开(公告)号：US20230298681A1

公开(公告)日：2023-09-21

申请号：US17655389

申请日：2022-03-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C29/12 ,  H03K3/037 ,  G06F1/06

CPC classification number: G11C29/12015 ,  H03K3/037 ,  G06F1/06 ,  G11C11/417

Abstract: Embodiments of the present disclosure provide a level-sensitive register unit, including: a data latch for receiving data; a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop; a first clock signal coupled to the data latch; and a second clock signal, wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.