公开(公告)号：US10553353B2

公开(公告)日：2020-02-04

申请号：US15355584

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Venkata N. R. Vanukuru

IPC: H01F5/00 ,  H01F41/04 ,  H01F17/00

Abstract: A high performance, on-chip a parallel stacked inductor which achieves a higher Q value. The inductor is formed on a layered substrate with a top metal layer having spiral winding conductive segments that terminate at an overpass junction, and a bottom metal layer traversing adjacent to, and parallel with, the top metal layer. The bottom metal layer having multiple bar vias imbedded therein for current carrying capabilities. The overpass junction having a width that is greater than the width of the adjacent spiral winding conductive segments.

公开(公告)号：US20180144857A1

公开(公告)日：2018-05-24

申请号：US15355584

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Venkata N. R. Vanukuru

IPC: H01F27/28 ,  H01F41/04

Abstract: A high performance, on-chip a parallel stacked inductor which achieves a higher Q value. The inductor is formed on a layered substrate with a top metal layer having spiral winding conductive segments that terminate at an overpass junction, and a bottom metal layer traversing adjacent to, and parallel with, the top metal layer. The bottom metal layer having multiple bar vias imbedded therein for current carrying capabilities. The overpass junction having a width that is greater than the width of the adjacent spiral winding conductive segments.

公开(公告)号：US20170084390A1

公开(公告)日：2017-03-23

申请号：US15370757

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert A. Groves ,  Sarath L. K. Parambil ,  Venkata N. R. Vanukuru

IPC: H01F41/06 ,  H01F27/28

CPC classification number: H01F41/06 ,  H01F17/0013 ,  H01F27/28 ,  H01F41/041 ,  H01F2017/002

Abstract: A three-dimensional multipath inductor includes turns disposed about a center region on two layers, the turns on the two layers having corresponding geometry therebetween. Each of the turns is comprised of two or more segments that extend length-wise along the turns, and the segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A lateral cross-over is configured to couple the segments of at least one turn on one layer with the segments on a turn on a same layer to form segment paths that have a substantially same length for all segment paths in a grouping of segment paths on that same layer. A vertical cross-over is configured to couple the segments on different vertically stacked metal layers to have the segment groups with a substantially same length for all segment paths based on vertical lengths.

公开(公告)号：US09479160B2

公开(公告)日：2016-10-25

申请号：US14573238

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Srihari ,  Venkata N. R. Vanukuru

IPC: H03K17/687 ,  H01Q1/50

CPC classification number: H03K17/687 ,  H01Q1/50 ,  H03K17/693 ,  H04B1/48

Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.

Abstract translation: RF通信收发器中的SPDT开关用于选择RF信号的发送/接收路径。 它由串联和分流支路组成，每个分支由堆叠的FET组成。 RF开关的性能指标是插入损耗和隔离。 在高频时，器件/ FET电容和寄生电容为信号提供了泄漏路径，导致更高的插入损耗和更低的隔离度。 与现有技术的SPDT开关相比，在SPDT开关中的串联和/或并联分支FET中的每一个上的并联谐振LC网络提供较低的插入损耗，更高的开关隔离和更低的带外谐波。 公开了一种减少这种开关配置的形状因子的方法，其在无线前端模块中是有用的。

公开(公告)号：US20160182037A1

公开(公告)日：2016-06-23

申请号：US14573238

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Srihari ,  Venkata N. R. Vanukuru

IPC: H03K17/687 ,  H01Q1/50

CPC classification number: H03K17/687 ,  H01Q1/50 ,  H03K17/693 ,  H04B1/48

Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.

Abstract translation: RF通信收发器中的SPDT开关用于选择RF信号的发送/接收路径。 它由串联和分流支路组成，每个分支由堆叠的FET组成。 RF开关的性能指标是插入损耗和隔离。 在高频时，器件/ FET电容和寄生电容为信号提供了泄漏路径，导致更高的插入损耗和更低的隔离度。 与现有技术的SPDT开关相比，在SPDT开关中的串联和/或并联分支FET中的每一个上的并联谐振LC网络提供较低的插入损耗，更高的开关隔离和更低的带外谐波。 公开了一种减少这种开关配置的形状因子的方法，其在无线前端模块中是有用的。

公开(公告)号：US10269735B1

公开(公告)日：2019-04-23

申请号：US16009329

申请日：2018-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Umesh Kumar Shukla ,  Sandeep Torgal ,  Venkata N. R. Vanukuru

IPC: H01L25/00 ,  H01L23/66 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H01L27/02 ,  H03H11/28 ,  H03H11/04 ,  G01R31/28

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure including: a first conductive layer of a device structure; a second conductive layer of the device structure vertically separated from the first conductive layer, wherein a load resistor couples the second conductive layer to ground; a t-coil having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer; and a variable capacitor having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer, the variable capacitor having an adjustable capacitance.