公开(公告)号：US10199315B2

公开(公告)日：2019-02-05

申请号：US15249700

申请日：2016-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta Ghate Farooq ,  John Matthew Safran

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.

公开(公告)号：US20180061749A1

公开(公告)日：2018-03-01

申请号：US15249700

申请日：2016-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta Ghate Farooq ,  John Matthew Safran

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5329

Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.