公开(公告)号：US08504867B2

公开(公告)日：2013-08-06

申请号：US12892854

申请日：2010-09-28

Applicant: Eric B Kushnick

Inventor： Eric B Kushnick

IPC: G06F1/24

CPC classification number: H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058 ,  H03K2005/00097 ,  H03L7/0812

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.