公开(公告)号：US09729305B2

公开(公告)日：2017-08-08

申请号：US14612218

申请日：2015-02-02

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chang Min Shin ,  Tae Ho Kim ,  Chae Deok Lim

IPC: H04L12/703 ,  H04L5/14 ,  H04W56/00 ,  B64D47/00

CPC classification number: H04L5/14 ,  B64D47/00 ,  H04W56/00

Abstract: Disclosed are an airplane system including duplex modules, and a control method thereof. The control method of the airplane system includes: receiving, by each of a plurality of duplex modules, a corresponding event command from a client; performing, by a first module, a first event specified by the event command in response to the event command; performing, by a second module different from the first module, a second event specified by the event command after the first event is completed; and returning a first response signal indicating a result of the performance of the first event and a second response signal indicating a result of the performance of the second event to the client, in which the client compares the first response signal and the second response signal, and determines whether the plurality of duplex modules is synchronized or has an error.

公开(公告)号：US10404393B2

公开(公告)日：2019-09-03

申请号：US15353764

申请日：2016-11-17

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young Mok Ha ,  Eun Ji Pak ,  Tae Ho Kim

IPC: H04J3/06 ,  H04L7/00

Abstract: A clock synchronization apparatus and method, which perform clock synchronization by determining a clock offset and a network delay between a master and a slave in an IEEE 1588 system. The clock synchronization method and apparatus include observing a clock offset and a packet delay using a timing packet received from a master node; estimating a clock offset and a packet delay from the observed clock offset and the observed packet delay; and performing synchronization with the master node based on the clock offset and the packet delay.