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    Semiconductor Temperature Sensor Using Bandgap Generator Circuit
    4.
    发明申请
    Semiconductor Temperature Sensor Using Bandgap Generator Circuit 有权
    使用带隙发生器电路的半导体温度传感器

    公开(公告)号：US20100283530A1

    公开(公告)日：2010-11-11

    申请号：US12841362

    申请日：2010-07-22

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: G05F1/10

    CPC classification number: G05F3/30

    Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

    Abstract translation: 公开了一种用于集成电路的组合带隙发生器和温度传感器。 本发明的实施例认识到，带隙发生器通常包含至少一个温度敏感元件，以便在带隙发生器产生的参考电压之外消除温度敏感性。 因此，根据本发明使用相同的温度敏感元件作为用于指示集成电路的温度的装置，而不需要制造分离和分离带隙发生器的温度传感器。 具体地，在一个实施例中，在组合带隙发生器和温度传感器电路的温度转换级部分中评估来自带隙发生器的温度敏感结两端的电压。 可以使用该电压的评估来产生指示集成电路的温度的基于电压或电流的输出，该输出本质上可以是二进制或模拟的。

    Measure control delay and method having latching circuit integral with delay circuit
    5.
    发明申请
    Measure control delay and method having latching circuit integral with delay circuit 有权

    公开(公告)号：US20070086250A1

    公开(公告)日：2007-04-19

    申请号：US11219302

    申请日：2005-09-01

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/135

    Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

    Access circuit and method for allowing external test voltage to be applied to isolated wells
    6.
    发明申请
    Access circuit and method for allowing external test voltage to be applied to isolated wells 失效
    访问电路和允许外部测试电压施加到隔离井的方法

    公开(公告)号：US20050146920A1

    公开(公告)日：2005-07-07

    申请号：US10748732

    申请日：2003-12-29

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: G11C11/22 ,  G11C29/50

    CPC classification number: G11C29/12005 ,  G11C5/066 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50016 ,  H01L27/0222 ,  H01L27/10897

    Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

    Abstract translation: 存取电路选择性地将外部可访问终端耦合到制造相应DRAM阵列的多个隔离DRAM阱中的每一个。 每个阱的存取电路包括在耦合在外部可访问的端子和相应的一个DRAM阱之间的各个阱中制造的第一和第二晶体管。 第一晶体管的阱耦合到外部可访问的端子，并且另一个晶体管的阱耦合到相应的DRAM阱。 控制电路将选择信号施加到第一和第二晶体管的栅电极。 控制电路包括各自的分流晶体管，当晶体管关断时，将栅极电极分流到第一和第二晶体管的源极区域，以将各个DRAM阱与外部端子隔离，而不管施加到...的测试电压的大小和极性如何 外部可访问终端。

    Temperature Compensation Via Power Supply Modification to Produce a Temperature-Independent Delay in an Integrated Circuit
    8.
    发明申请
    Temperature Compensation Via Power Supply Modification to Produce a Temperature-Independent Delay in an Integrated Circuit 有权
    通过电源修改实现温度补偿，以在集成电路中产生与温度无关的延迟

    公开(公告)号：US20110187441A1

    公开(公告)日：2011-08-04

    申请号：US13087654

    申请日：2011-04-15

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: H01L35/00

    CPC classification number: H03L7/0812 ,  H03L1/022 ,  H03L7/0814

    Abstract: A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. In accordance with embodiments of the invention, such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit, and hence the VDL, delay element, or subcircuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, which otherwise would increase the delay though the VDL, delay element, or subcircuit, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature. Through this scheme, and assuming the temperature sensing stage is properly tuned, temperature-dependent delays can be reduced to approximately zero.

    Abstract translation: 公开了一种用于调整延迟锁定环（DLL）中的可变延迟线（VDL）或集成电路上的其他延迟元件或分支电路的延迟的方法和电路。 这种延迟电路固有地具有作为温度的函数的延迟。 根据本发明的实施例，通过调节VDL，延迟元件或子电路的电源电压来补偿这种依赖于温度的延迟。 具体地，使用温度感测级来感测集成电路的温度，并因此检测VDL，延迟元件或子电路。 关于感测温度的信息被发送到从集成电路的主电源电压Vcc导出本地电源电压的调节器。 如果感测到的温度相对较高，否则会增加VDL，延迟元件或分支电路的延迟，调节器会增加本地电源电压，从而减少延迟并抵消由于温度引起的延迟增加。 通过该方案，假设温度感测级被适当地调节，温度依赖的延迟可以减少到大约为零。

    Semiconductor temperature sensor using bandgap generator circuit
    9.
    发明授权
    Semiconductor temperature sensor using bandgap generator circuit 有权
    半导体温度传感器采用带隙发生器电路

    公开(公告)号：US07978000B2

    公开(公告)日：2011-07-12

    申请号：US12841362

    申请日：2010-07-22

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: H01L5/00

    CPC classification number: G05F3/30

    Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

    Abstract translation: 公开了一种用于集成电路的组合带隙发生器和温度传感器。 本发明的实施例认识到，带隙发生器通常包含至少一个温度敏感元件，以便在带隙发生器产生的参考电压之外消除温度敏感性。 因此，根据本发明，使用相同的温度敏感元件作为用于指示集成电路的温度的装置，而不需要制造分离和分离带隙发生器的温度传感器。 具体地，在一个实施例中，在组合带隙发生器和温度传感器电路的温度转换级部分中评估来自带隙发生器的温度敏感结两端的电压。 可以使用该电压的评估来产生指示集成电路的温度的基于电压或电流的输出，该输出本质上可以是二进制或模拟的。

    Temperature compensation via power supply modification to produce a temperature-independent delay in an integrated circuit
    10.
    发明授权
    Temperature compensation via power supply modification to produce a temperature-independent delay in an integrated circuit 有权
    通过电源修改进行温度补偿，以在集成电路中产生与温度无关的延迟

    公开(公告)号：US07936203B2

    公开(公告)日：2011-05-03

    申请号：US11351037

    申请日：2006-02-08

    Applicant: David Zimlich

    Inventor： David Zimlich

    IPC: H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78

    CPC classification number: H03L7/0812 ,  H03L1/022 ,  H03L7/0814

    Abstract: A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. In accordance with embodiments of the invention, such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit, and hence the VDL, delay element, or subcircuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, which otherwise would increase the delay though the VDL, delay element, or subcircuit, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature. Through this scheme, and assuming the temperature sensing stage is properly tuned, temperature-dependent delays can be reduced to approximately zero.

    Abstract translation: 公开了一种用于调整延迟锁定环（DLL）中的可变延迟线（VDL）或集成电路上的其他延迟元件或分支电路的延迟的方法和电路。 这种延迟电路固有地具有作为温度的函数的延迟。 根据本发明的实施例，通过调节VDL，延迟元件或子电路的电源电压来补偿这种依赖于温度的延迟。 具体地，使用温度感测级来感测集成电路的温度，并因此检测VDL，延迟元件或子电路。 关于感测温度的信息被发送到从集成电路的主电源电压Vcc导出本地电源电压的调节器。 如果感测到的温度相对较高，否则会增加通过VDL，延迟元件或分支电路的延迟，调节器增加局部电源电压，从而减小延迟并抵消由于温度引起的延迟增加。 通过该方案，假设温度感测级被适当地调节，温度依赖的延迟可以减少到大约为零。

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