公开(公告)号：US08645891B2

公开(公告)日：2014-02-04

申请号：US13835398

申请日：2013-03-15

Applicant: Dainippon Screen Mfg. Co., Ltd.

Inventor： Kiyoshi Kitamura ,  Kazuhiro Nakai

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: It is an object to generate wiring data while controlling generation of omission of wiring and shortening process time. In order to achieve this object, a device for generating wiring data includes: an error acquiring part that acquires a configuration error of the semiconductor chip relative to a certain reference position and a certain reference angle on the substrate; an area information acquiring part that acquires enclosing area information indicating an enclosing area enclosing the semiconductor chip on the substrate; and a wiring data generating part that generates enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip free from a configuration error and being a part of a reference wiring pattern free from faulty wiring. The enclosing area wiring pattern is a part of the connection wiring pattern and covers the enclosing area. The wiring data generating part generates the enclosing area wiring data such that the position and the angle of the reference fan-out line relative to the reference chip, and the position and the angle of a fan-out line for the semiconductor chip on the substrate relative to this semiconductor chip, agree with each other independently of the configuration error.

Abstract translation: 本发明的目的是在控制线路的省略和缩短处理时间的同时产生布线数据。 为了实现该目的，用于产生布线数据的装置包括：误差获取部，其获取半导体芯片相对于基板上的某个基准位置和特定基准角度的配置误差; 区域信息获取部，其获取表示在所述基板上包围所述半导体芯片的封闭区域的封闭区域信息; 以及布线数据生成部，其基于对于没有配置误差而构成的基准芯片的基准扇出线，生成表示封闭区域布线图案的封闭区域布线数据，并且是没有错误布线的基准布线图案的一部分。 封闭区域布线图案是连接布线图案的一部分并且覆盖封闭区域。 布线数据生成部生成包围区域配线数据，使得基准扇出线相对于基准芯片的位置和角度以及衬底上半导体芯片的扇出线的位置和角度 相对于该半导体芯片，独立于配置错误彼此一致。