公开(公告)号：US10672624B2

公开(公告)日：2020-06-02

申请号：US16012678

申请日：2018-06-19

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  William Boyd Rogers ,  Craig Bishop

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H01L21/78 ,  H01L21/52 ,  H01L23/31 ,  H01L25/10 ,  H01L21/304

Abstract: A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.

公开(公告)号：US10050004B2

公开(公告)日：2018-08-14

申请号：US15356208

申请日：2016-11-18

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  William Boyd Rogers ,  Craig Bishop

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/373 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

Abstract: A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

公开(公告)号：US20170148755A1

公开(公告)日：2017-05-25

申请号：US15356208

申请日：2016-11-18

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  William Boyd Rogers ,  Craig Bishop

IPC: H01L23/00 ,  H01L23/373 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L24/19 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3731 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

公开(公告)号：US09613912B2

公开(公告)日：2017-04-04

申请号：US14971458

申请日：2015-12-16

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan

IPC: H01L21/46 ,  H01L23/544 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/11 ,  H01L2224/03

Abstract: A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

公开(公告)号：US20170084596A1

公开(公告)日：2017-03-23

申请号：US15268345

申请日：2016-09-16

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan

IPC: H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/09 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.

公开(公告)号：US20160329257A1

公开(公告)日：2016-11-10

申请号：US15213291

申请日：2016-07-18

Applicant: DECA TECHNOLOGIES INC.

Inventor： Christopher M. Scanlan ,  Craig Bishop

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3135 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/0217 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/117 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8212 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.

公开(公告)号：US20160260682A1

公开(公告)日：2016-09-08

申请号：US15151384

申请日：2016-05-10

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  William Boyd Rogers ,  Craig Bishop

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/52

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/0231 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L21/304 ,  H01L23/3164 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive interconnects over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted at the semiconductor die mounting site. The conductive interconnects and semiconductor die can be encapsulated with mold compound. First ends of the conductive interconnects can be exposed. The temporary carrier can be removed to expose second ends of the conductive interconnects opposite the first ends of the conductive interconnects. The conductive interconnects can be etched to recess the second ends of the conductive interconnects with respect to the mold compound. The conductive interconnects can comprise a first portion, a second portion, and an etch stop layer disposed between the first portion and the second portion.

Abstract translation: 制造半导体器件的方法可以包括提供具有半导体管芯安装位置的临时载体，并且在半导体管芯安装位置的周围在临时载体上形成导电互连。 半导体管芯可以安装在半导体管芯安装位置。 导电互连和半导体管芯可以用模具化合物封装。 可以暴露导电互连的第一端。 可以移除临时载体以暴露与导电互连的第一端相对的导电互连的第二端。 可以蚀刻导电互连以相对于模具化合物凹进导电互连的第二端。 导电互连可以包括设置在第一部分和第二部分之间的第一部分，第二部分和蚀刻停止层。

公开(公告)号：US09337086B2

公开(公告)日：2016-05-10

申请号：US14584978

申请日：2014-12-29

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L21/76838 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/20 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/19 ,  H01L23/3164 ,  H01L2224/03

Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.

公开(公告)号：US09269622B2

公开(公告)日：2016-02-23

申请号：US13891056

申请日：2013-05-09

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  Timothy L. Olson

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).

Abstract translation: 描述制造半导体器件的半导体器件和方法。 提供了一种嵌入式模具面板，其包括由锯片隔开的多个半导体模具。 通过化学镀处理形成导电层，导电层包括布置在锯条街道中的总线和耦合到半导体管芯和总线的再分配层（RDL）。 绝缘层形成在导电层和嵌入的模板上，绝缘层包括设置在半导体管芯的覆盖区外的导电层上的开口。 通过使用导电层作为电镀工艺的一部分，在绝缘层的开口中形成互连结构。 在形成互连结构之后，将嵌入式模具面板通过锯条划分，以去除总线和来自各个扇出的晶片级封装（FOWLP）。

公开(公告)号：US20140225271A1

公开(公告)日：2014-08-14

申请号：US14261265

申请日：2014-04-24

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan

IPC: H01L23/29 ,  H01L23/528

CPC classification number: H01L23/293 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2224/82 ,  H01L2924/00

Abstract: Panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die unit in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less pattering technique.

Abstract translation: 描述了在电介质膜上放置多个管芯单元的面板封装。 然后固化电介质膜以将多个模具单元锁定就位，然后将其封装。 然后使用无掩模图案技术将固化的电介质膜图案化。