System and method for measuring a capacitance by transferring charge from a fixed source
    1.
    发明授权
    System and method for measuring a capacitance by transferring charge from a fixed source 有权
    通过从固定源传输电荷来测量电容的系统和方法

    公开(公告)号:US07863909B2

    公开(公告)日:2011-01-04

    申请号:US12042217

    申请日:2008-03-04

    Applicant: Colby Keith

    Inventor: Colby Keith

    CPC classification number: H03K17/962 H03K2217/960725

    Abstract: A touch sensor device and method is provided that determines measurable capacitances for object detection. The systems and methods measure capacitance by controllably transferring charge from a storage capacitor, and determining the measurable capacitance by measuring the residual voltage remaining on the storage capacitor after the transfer. The systems and methods thus provide an accurate determination of the measurable capacitance that can be used for object proximity sensing.

    Abstract translation: 提供了一种触摸传感器装置和方法,其确定用于物体检测的可测量的电容。 系统和方法通过可控地从存储电容器传送电荷来测量电容,并且通过测量传输后的存储电容器上剩余的残余电压来确定可测量的电容。 因此,系统和方法可以准确地确定可用于物体接近感测的可测电容。

    CIRCUITS AND METHODS TO GUARANTEE LOCK IN DELAY LOCKED LOOPS AND AVOID HARMONIC LOCKING
    2.
    发明申请
    CIRCUITS AND METHODS TO GUARANTEE LOCK IN DELAY LOCKED LOOPS AND AVOID HARMONIC LOCKING 审中-公开
    电路和保护锁定延迟锁定的方法和避免谐波锁定

    公开(公告)号:US20130271193A1

    公开(公告)日:2013-10-17

    申请号:US13532241

    申请日:2012-06-25

    Applicant: Colby Keith

    Inventor: Colby Keith

    CPC classification number: H03L7/0812 H03L7/0816 H03L7/089 H03L7/093 H03L7/10

    Abstract: A delay locked loop (DLL) includes a phase detector (PD), a lock assistor (LA), a control voltage generator, and a voltage controlled delay line (VCDL). The PD determines a phase difference between of a reference clock and a delayed version of the reference clock and produces a pair of phase detector output signals in dependence on the determined phase difference. The LA receives the pair of phase detector output signals and produces a pair of lock assist output signals by selectively swapping the phase detector output signals. The control voltage generator receives the pair of lock assist output signals and produces a control voltage signal in dependence on thereon. The VCDL receives the control voltage signal and the reference clock (or a buffered version thereof) and outputs the delayed version of the reference clock, with a delay through the VCDL being dependent on the received control voltage signal.

    Abstract translation: 延迟锁定环路(DLL)包括相位检测器(PD),锁相器(LA),控制电压发生器和电压控制延迟线(VCDL)。 PD确定参考时钟和参考时钟的延迟版本之间的相位差,并根据所确定的相位差产生一对相位检测器输出信号。 LA通过选择性地交换相位检测器输出信号,接收一对相位检测器输出信号并产生一对锁定辅助输出信号。 控制电压发生器接收一对锁定辅助输出信号,并根据其产生控制电压信号。 VCDL接收控制电压信号和参考时钟(或其缓冲版本),并输出参考时钟的延迟版本,通过VCDL的延迟取决于接收到的控制电压信号。

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