公开(公告)号：US08872228B2

公开(公告)日：2014-10-28

申请号：US13469526

申请日：2012-05-11

Applicant: Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

Inventor： Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.

Abstract translation: 公开了一种用于控制IC器件应变的方法和由此形成的器件。 示例性实施例包括接收具有对应于IC器件的器件区域的IC器件衬底。 在器件区域内形成非晶区域的器件区域上进行注入工艺。 IC器件衬底被凹入以在器件区域中限定具有由非晶区域的无定形结构确定的分布的源极/漏极凹部。 然后进行源极/漏极外延，以在源极/漏极凹部内形成源极/漏极结构。

公开(公告)号：US08680625B2

公开(公告)日：2014-03-25

申请号：US12905579

申请日：2010-10-15

Applicant: Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

Inventor： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC: H01L27/088

CPC classification number: H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

Abstract translation: 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US08614132B2

公开(公告)日：2013-12-24

申请号：US13240025

申请日：2011-09-22

Applicant: Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

Inventor： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC: H01L21/336

CPC classification number: H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US08580641B2

公开(公告)日：2013-11-12

申请号：US13191297

申请日：2011-07-26

Applicant: Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

Inventor： Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/70 ,  H01L21/8234

CPC classification number: H01L27/11 ,  H01L21/28176 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7827

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.

公开(公告)号：US08535998B2

公开(公告)日：2013-09-17

申请号：US12720075

申请日：2010-03-09

Applicant: Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L21/338

CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

Abstract translation: 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US08482079B2

公开(公告)日：2013-07-09

申请号：US13161031

申请日：2011-06-15

Applicant: Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

Inventor： Chun-Fai Cheng ,  Li-Ping Huang ,  Ka-Hing Fung

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66666 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed device comprises a gate structure over a substrate and defining a channel region in the substrate, an epitaxial feature with a first dopant in the substrate, and an epitaxial source/drain feature with a second dopant in the substrate. The epitaxial source/drain feature is farther from the channel region than the epitaxial feature is. The second dopant has an electrical carrier type opposite to the first dopant.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的器件包括在衬底上的栅极结构并且限定衬底中的沟道区，在衬底中具有第一掺杂剂的外延特征以及在衬底中具有第二掺杂剂的外延源极/漏极特征。 外延源极/漏极特征比沟道区域远离外延特征。 第二掺杂剂具有与第一掺杂剂相反的电载体。

公开(公告)号：US09698054B2

公开(公告)日：2017-07-04

申请号：US12984703

申请日：2011-01-05

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Li-Ping Huang ,  Wei-Yuan Lu

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Li-Ping Huang ,  Wei-Yuan Lu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636

Abstract: In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity.

公开(公告)号：US09311845B2

公开(公告)日：2016-04-12

申请号：US14071169

申请日：2013-11-04

Applicant: Chun-Fai Cheng

Inventor： Chun-Fai Cheng

IPC: G09G3/32 ,  G09G3/30 ,  G09G3/36

CPC classification number: G09G3/32 ,  G09G3/30 ,  G09G3/3614 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2320/0276

Abstract: A circuit and method of driving a display panel requiring gray scale control wherein the voltage applied to a row of pixels is equal to the sum of voltages of opposite sign with respect to ground applied respectively to the row electrode and column electrodes whose intersection with the row defines the pixels. Gray scale is realized through modulation of the voltage applied to the column electrodes. Typically for video application, 256 individual gray levels are required corresponding to luminance levels ranging from zero (no emissive luminance) to full luminance. The required luminance for each gray level is not a linear function of the gray level number but rather corresponds to an approximate quadratic function of this number. The present invention facilitates generation of luminance values for each gray level that approximates this functional dependence (i.e. Gamma corrected) with a non-linear voltage ramp terminated by a digital clock having 256 (8 bit) resolution. The voltage at the ramp termination is held at a constant value and fed to the output buffer of the gray scale drivers for the display columns.

Abstract translation: 驱动需要灰度控制的显示面板的电路和方法，其中施加到一行像素的电压等于分别施加到相对于地面的相对符号的电压之和，与行电极和列电极的与行的交点相加 定义像素。 通过调制施加到列电极的​​电压来实现灰度级。 通常对于视频应用，需要对应于从零（无发光亮度）到全亮度的亮度级别需要256个单独的灰度级。 每个灰度级的所需亮度不是灰度级数的线性函数，而是对应于该数的近似二次函数。 本发明有助于以由具有256（8位）分辨率的数字时钟终止的非线性电压斜坡来生成近似该功能依赖性（即，伽马校正）的每个灰度级的亮度值。 斜坡端接电压保持恒定值，并送到显示列的灰度级驱动器的输出缓冲器。

公开(公告)号：US20140021517A1

公开(公告)日：2014-01-23

申请号：US13551107

申请日：2012-07-17

Applicant: Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

Inventor： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 在衬底中形成隔离结构，并且在隔离结构的顶部形成栅叠层。 邻接栅叠层的侧壁并且延伸超出隔离结构的边缘的间隔件。 所公开的方法提供了通过使用间隔物来保护隔离结构的改进方法。 间隔件可以防止隔离结构被化学物质损坏，从而增强接触着陆和提升设备性能。

公开(公告)号：US08569139B2

公开(公告)日：2013-10-29

申请号：US12913041

申请日：2010-10-27

Applicant: Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

Inventor： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

IPC: H01L21/336 ,  H01L21/461

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.