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1.发明授权公开(公告)号：US07616722B2
公开(公告)日：2009-11-10
申请号：US11148852
申请日：2005-06-08
IPC: H04L7/00
CPC classification number: H04L7/02
Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.
Abstract translation: 提供了一种在时钟数据恢复系统中提取时钟的方法。 该方法包括以下步骤。 首先，对多个串行链路发送数据进行采样，生成多个脉冲信号并依次排列。 然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。 预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。 然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。 最后，当生成在预定次数内没有数据状态改变的脉冲信号时，提取时钟。
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公开(公告)号：US20090074121A1
公开(公告)日：2009-03-19
申请号：US12273230
申请日：2008-11-18
IPC: H04L7/00
CPC classification number: H04L7/02
Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.
Abstract translation: 提供了一种在时钟数据恢复系统中提取时钟的方法。 该方法包括以下步骤。 首先，对串行链路发送数据进行多次采样，生成并顺序排列多个脉冲信号。 然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。 预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。 然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。 最后，当在预定次数内不产生数据状态改变的脉冲信号时，提取时钟。
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公开(公告)号：US07643594B2
公开(公告)日：2010-01-05
申请号：US12273230
申请日：2008-11-18
IPC: H04L7/00
CPC classification number: H04L7/02
Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.
Abstract translation: 提供了一种在时钟数据恢复系统中提取时钟的方法。 该方法包括以下步骤。 首先，对串行链路发送数据进行多次采样，生成并顺序排列多个脉冲信号。 然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。 预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。 然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。 最后，当在预定次数内产生无数据状态改变的脉冲信号时，提取时钟。
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公开(公告)号：US20060188047A1
公开(公告)日：2006-08-24
申请号：US11148852
申请日：2005-06-08
CPC classification number: H04L7/02
Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.
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