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    Multiple die paddle leadframe and semiconductor device package
    1.
    发明授权
    Multiple die paddle leadframe and semiconductor device package 有权
    多芯片引线框和半导体器件封装

    公开(公告)号：US08436460B1

    公开(公告)日：2013-05-07

    申请号：US11894513

    申请日：2007-08-20

    Applicant: Carlo Gamboa ,  Bo Chang

    Inventor： Carlo Gamboa ,  Bo Chang

    IPC: H01L23/48

    CPC classification number: H01L23/49503 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.

    Abstract translation: 公开了一种具有用于接受多个半导体器件的多个半导体器件管芯焊盘的引线框架和半导体器件封装，其中引线框架通过将多个管芯集成到具有相对较小的占位面积的半导体器件封装中来增加半导体器件密度并降低成本。 引线框架可以包括至少一个全金属模板和至少一个还原金属模板，其可以形成统一的或混合的模板。 引线框架可以实现多个半导体器件到公共引线键盘和/或管芯焊盘的电耦合，其中耦合到公共引线引脚和/或管芯焊盘的内部引线管可以从半导体器件接收电耦合装置。 引线框架的一个或多个管芯焊盘的表面可以暴露于半导体器件封装的外部，以实现连接到引线框架的一个或多个半导体器件的电气测试和/或提供散热。

    Warpage-compensating die paddle design for high thermal-mismatched package construction
    2.
    发明授权
    Warpage-compensating die paddle design for high thermal-mismatched package construction 有权
    翘曲补偿芯片设计用于高热失配封装结构

    公开(公告)号：US08017445B1

    公开(公告)日：2011-09-13

    申请号：US11803475

    申请日：2007-05-15

    Applicant: Bo Chang ,  Carlo Gamboa

    Inventor： Bo Chang ,  Carlo Gamboa

    IPC: H01L23/495 ,  H01L21/60

    CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.

    Abstract translation: 公开了用于半导体器件和集成电路的方法和封装，其消除了由器件，引线框架或管芯焊盘与模制化合物之间的热膨胀系数（CTE）失配引起的封装上的翘曲应力。 通常，该方法包括以下步骤：（i）将其上制造器件的管芯安装到引线框架的管芯焊盘上; 和（ii）将模具封装在模具板上以及至少一部分引线框架在模制化合物中，其中在引线框架的平面上方的第一体积的模塑料和在平面之下的第二体积的模塑料之间的差异 引线框架和包装化合物的CTE不匹配，从而充分降低了引线框架的基本消除了成品封装的翘曲。 可以蚀刻或还原模板以便于在引线框架的平面下流动的模塑料。 还公开了其他实施例。

    Integrated circuit package and packaging method
    3.
    发明授权
    Integrated circuit package and packaging method 有权
    集成电路封装和封装方法

    公开(公告)号：US08106489B1

    公开(公告)日：2012-01-31

    申请号：US12154775

    申请日：2008-05-27

    Applicant: Carlo Gamboa ,  Salvador Padre

    Inventor： Carlo Gamboa ,  Salvador Padre

    IPC: H01L23/48

    CPC classification number: H01L23/4951 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.

    Abstract translation: 提供了一种包装和包装方法，其可以包装较大的模具和/或较小的包装。 通常，该方法包括以下步骤：（i）减小延伸到形成的封装中的引线框的引线顶表面的一部分的厚度; （ii）将模具安装到引线框架的桨叶上，模具延伸通过桨叶的边缘进入通过减小引线的厚度而产生的空间; 和（iii）将模具和引线框架（包括引线的减少部分）封装在模塑料中。 在一个实施例中，通过半蚀刻顶表面的部分来减少引线。 优选地，所述方法还包括在所述管芯上的引线接合焊盘，以将所述引线的蚀刻部分电连接到所述引线。 或者，引线接合位于引线的焊盘和非蚀刻部分之间。 还公开了其他实施例。

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