公开(公告)号：US20220216304A1

公开(公告)日：2022-07-07

申请号：US17562164

申请日：2021-12-27

Applicant: Cambridge Electronics, Inc.

Inventor： Bin Lu

IPC: H01L29/10 ,  H01L29/45 ,  H01L29/20 ,  H01L29/778 ,  H01L29/47 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

Abstract: This disclosure describes the structure and technology to modify the distribution of channel electron density underneath the gate electrode of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed in the gate region of the transistor structure. In certain embodiments, the EDR regions are created using recesses. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. The gate electrode may make Schottky contact with the barrier layer and the EDR regions, or a dielectric layer may be disposed in the gate region.

公开(公告)号：US09614069B1

公开(公告)日：2017-04-04

申请号：US15376826

申请日：2016-12-13

Applicant: Cambridge Electronics, Inc.

Inventor： Bin Lu ,  Ling Xia

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/7783 ,  H01L29/7787

Abstract: A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

公开(公告)号：US20170018617A1

公开(公告)日：2017-01-19

申请号：US15213054

申请日：2016-07-18

Applicant: Cambridge Electronics, Inc.

Inventor： Ling Xia ,  Mohamed Azize ,  Bin Lu

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/861 ,  H01L29/45 ,  H01L49/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/861 ,  H01L29/94

Abstract: Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

Abstract translation: 公开了用于半导体器件中的电场管理的场板结构。 场板半导体结构包括半导体衬底，源欧姆接触，漏极欧姆接触和设置在源极欧姆接触和漏极欧姆接触之间的栅极区域上的栅极接触，以及连接到源极的源极场 欧姆接触。 场致电介质设置在半导体衬底之上。 封装电介质设置在栅极触点上方，其中封装电介质覆盖栅极触点的顶表面。 源场板在场板区域中设置在场板电介质上，不存在封装电介质。

公开(公告)号：US20160300835A1

公开(公告)日：2016-10-13

申请号：US15094985

申请日：2016-04-08

Applicant: Cambridge Electronics, Inc.

Inventor： Ling Xia ,  Mohamed Azize ,  Bin Lu

IPC: H01L27/088 ,  H01L21/8252 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/66704 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0883 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66621 ,  H01L29/66734 ,  H01L29/7787

Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0≦x, y, z≦1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0

Abstract translation: 公开了半导体结构，用于在公共衬底上将具有不同阈值电压的多个III-N晶体管单片集成。 半导体结构包括包含多个可选择性蚀刻的子层的覆盖层，其中每个子层相对于紧下方的子层可选择性地蚀刻，其中每个子层包括材料Al x In y Ga z N（0≤x，y，z≤1），并且其中 至少一个可选择性蚀刻的子层具有非零的Ga含量（0

公开(公告)号：US09455342B2

公开(公告)日：2016-09-27

申请号：US14550730

申请日：2014-11-21

Applicant: Cambridge Electronics, Inc.

Inventor： Bin Lu ,  Tomas Palacios ,  Ling Xia ,  Mohamed Azize

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/405 ,  H01L29/41725

Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.

Abstract translation: 半导体器件包括衬底，第一有源层，第二有源层，至少第一和第二电极，E场管理层和至少一个注入电极。 第一有源层设置在衬底上。 第二有源层设置在第一有源层上，使得出现沿横向方向延伸的横向延伸的导电通道。 横向延伸的导电通道位于第一有源层和第二有源层之间。 第一和第二电极电连接到第一有源层。 减少在第一和第二有源层中出现的电场梯度的电场管理层设置在第二有源层上。 注入电极与E场管理层电连接。

公开(公告)号：US12080807B2

公开(公告)日：2024-09-03

申请号：US17350563

申请日：2021-06-17

Applicant: Cambridge Electronics, Inc.

Inventor： Dongfei Pei ,  Bin Lu

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/207 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402

Abstract: This disclosure describes the structure and technology to modify the free electron density between the anode electrode and cathode electrode of III-nitride semiconductor diodes. Electron density reduction regions (EDR regions) are disposed between the anode and cathode electrodes of the diode structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

公开(公告)号：US11349003B2

公开(公告)日：2022-05-31

申请号：US15931744

申请日：2020-05-14

Applicant: Cambridge Electronics, Inc.

Inventor： Bin Lu

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L21/108 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate region.

公开(公告)号：US20210399145A1

公开(公告)日：2021-12-23

申请号：US17350563

申请日：2021-06-17

Applicant: Cambridge Electronics, Inc.

Inventor： Dongfei Pei ,  Bin Lu

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/40 ,  H01L29/207

Abstract: This disclosure describes the structure and technology to modify the free electron density between the anode electrode and cathode electrode of III-nitride semiconductor diodes. Electron density reduction regions (EDR regions) are disposed between the anode and cathode electrodes of the diode structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

公开(公告)号：US09911817B2

公开(公告)日：2018-03-06

申请号：US15213054

申请日：2016-07-18

Applicant: Cambridge Electronics, Inc.

Inventor： Ling Xia ,  Mohamed Azize ,  Bin Lu

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/86 ,  H01L49/02 ,  H01L29/861 ,  H01L29/778 ,  H01L29/94 ,  H01L29/20 ,  H01L29/45 ,  H01L29/417 ,  H01L29/47

CPC classification number: H01L29/404 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/861 ,  H01L29/94

Abstract: Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

公开(公告)号：US09754937B1

公开(公告)日：2017-09-05

申请号：US15449391

申请日：2017-03-03

Applicant: Cambridge Electronics, Inc.

Inventor： Bin Lu ,  Ling Xia

IPC: H01L27/088 ,  H01L21/336 ,  H03K17/687 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7819 ,  H03K17/102 ,  H03K17/284 ,  H03K17/687 ,  H03K17/6871 ,  H03K2017/6875

Abstract: A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.