公开(公告)号：US20170294218A1

公开(公告)日：2017-10-12

申请号：US15614450

申请日：2017-06-05

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1697

Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.

公开(公告)号：US09728240B2

公开(公告)日：2017-08-08

申请号：US14214064

申请日：2014-03-14

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1677

Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.

公开(公告)号：US20170162242A1

公开(公告)日：2017-06-08

申请号：US15434966

申请日：2017-02-16

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C7/04 ,  G11C11/1695 ,  G11C11/1697 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.

公开(公告)号：US20160254046A1

公开(公告)日：2016-09-01

申请号：US15148694

申请日：2016-05-06

Applicant: Avalanche Technology, Inc.

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/56 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.

Abstract translation: 本发明涉及一种多状态电流切换磁存储元件，其被配置为通过流过其中的电流来存储状态，以切换包括在顶电极和底电极之间并联耦合的两个或更多个磁隧道结（MTJ）的状态 。 每个MTJ包括具有垂直于其层平面的可切换磁性取向的自由层，具有垂直于其层平面的固定磁方位的固定层和插入在自由层和固定层之间的阻挡层。 磁存储元件可操作以存储多于一位的信息。

公开(公告)号：US20150146482A1

公开(公告)日：2015-05-28

申请号：US14599450

申请日：2015-01-16

Applicant: Avalanche Technology, Inc.

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  H01L43/02

Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.

Abstract translation: 具有使用MTJ的磁状态读取的磁性隧道结（MTJ）的磁性随机存取存储器（MRAM）阵列，通过在其上施加电流读取MTJ。 此外，MRAM阵列具有参考MTJ，耦合到MTJ的读出放大器和参考MTJ，读出放大器可用于在确定MTJ的状态时将MTJ的电压与参考MTJ进行比较; 在第一端耦合到读出放大器并在第二端接地的第一电容器; 以及第二电容器，其在第一端处耦合到所述读出放大器并在第二端接地，所述第一电容器存储所述第一电容器，其中当读取所述MTJ时，将短电压脉冲施加到所述第一和第二电容器的每一个的第一端，从而 使电流通过MTJ在那里通过一小段时间间隔，从而避免对MTJ的读取干扰。

公开(公告)号：US20140185372A1

公开(公告)日：2014-07-03

申请号：US14201374

申请日：2014-03-07

Applicant: Avalanche Technology, Inc.

Inventor： Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/08 ,  G11C11/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5607 ,  G11C13/004

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract translation: 感测电路包括具有第一和第二节点的读出放大器电路，通过该第一和第二节点检测磁存储元件。 第一电流源耦合到第一节点，第二电流源耦合到第二节点。 参考磁存储元件具有与之相关联的电阻并且耦合到第一节点，参考磁存储元件从第一电流源接收电流。 具有与其相关联的电阻的至少一个存储元件耦合到第二节点并从第二电流源接收电流。 来自第一电流源的电流和来自第二电流源的电流基本相同。 通过比较至少一个存储元件的电阻与参考磁存储元件的电阻来感测至少一个存储元件的逻辑状态。

公开(公告)号：US08730716B2

公开(公告)日：2014-05-20

申请号：US13931596

申请日：2013-06-28

Applicant: Avalanche Technology, Inc.

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: H01L43/12 ,  G06F17/30038

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属，并且形成在存取晶体管的顶部。 磁性隧道结（MTJ）形成在形成在靠近位线的ILD层中的金属的顶部上。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US08724379B2

公开(公告)日：2014-05-13

申请号：US13857857

申请日：2013-04-05

Applicant: Avalanche Technology, Inc.

Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US08542526B2

公开(公告)日：2013-09-24

申请号：US13763512

申请日：2013-02-08

Applicant: Avalanche Technology, Inc.

Inventor： Parviz Keshtbod ,  Roger Klas Malmhall ,  Rajiv Yadav Ranjan

IPC: G11C11/00

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

Abstract translation: 制造磁性随机存取存储单元的方法包括在晶片的顶部形成磁性隧道结（MTJ），在MTJ的顶部上沉积氧化物，在氧化物层的顶部上沉积光致抗蚀剂层，形成沟槽 所述光刻胶层和所述沟槽的宽度与所述MTJ的宽度基本相同的氧化物层。 然后，除去光致抗蚀剂层，并且在沟槽中的氧化物层的顶部上沉积硬掩模层，并且平坦化晶片以去除不在沟槽中的硬掩模层的部分以使顶部基本上平坦 的氧化物层和硬质层。 蚀刻剩余的氧化物层，并蚀刻MTJ以除去未被硬掩模层覆盖的MTJ的部分。

公开(公告)号：US20130107613A1

公开(公告)日：2013-05-02

申请号：US13720291

申请日：2012-12-19

Applicant: Avalanche Technology, Inc.

Inventor： Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.