公开(公告)号：US11610533B2

公开(公告)日：2023-03-21

申请号：US17469216

申请日：2021-09-08

Applicant: AU Optronics Corporation

Inventor： Che-Chia Chang ,  Yi-Jung Chen ,  Shang-Jie Wu ,  Yu-Chieh Kuo ,  Hsien-Chun Wang ,  Ming-Hung Chuang ,  Mei-Yi Li ,  He-Yi Cheng ,  Yi-Fan Chen

IPC: G09G3/30

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

公开(公告)号：US11443675B2

公开(公告)日：2022-09-13

申请号：US17468720

申请日：2021-09-08

Applicant: AU Optronics Corporation

Inventor： Che-Chia Chang ,  Yi-Jung Chen ,  Shang-Jie Wu ,  Yu-Chieh Kuo ,  Hsien-Chun Wang ,  Ming-Hung Chuang ,  Mei-Yi Li ,  Sin-An Lin ,  Chen-Ying Chou

IPC: G09G3/36 ,  G09G3/20 ,  G11C19/28

Abstract: A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other.

公开(公告)号：US10909944B2

公开(公告)日：2021-02-02

申请号：US15981900

申请日：2018-05-17

Applicant: Au Optronics Corporation

Inventor： Che-Chia Chang ,  Chun-Ru Huang ,  Ming-Hung Chuang

IPC: G09G3/36 ,  H01L27/12

Abstract: A display panel and a pixel circuit thereof are provided. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits. Each of the pixel circuits is coupled to corresponding gate line and data line. Each of the pixel circuits includes a first gate line and a pull-low switch. The first gate line is coupled to a control terminal of a driving transistor, and provides a first gate signal to drive the driving transistor during a driving time period. The pull-low switch pulls low the first gate signal to a reference low voltage according to a second gate signal on a second gate line when the driving time period finishes.

公开(公告)号：US20200273884A1

公开(公告)日：2020-08-27

申请号：US16451020

申请日：2019-06-25

Applicant: Au Optronics Corporation

Inventor： Yao-Jiun Tsai ,  Ming-Hung Chuang

IPC: H01L27/12 ,  G02F1/1362 ,  G06F3/041

Abstract: A pixel array substrate includes a substrate, pixels, and connection wires. The substrate has a transparent window, a wire region, and an active region. The connection wires are disposed in the wire region. Each connection wire is electrically connected to first signal lines of the pixels respectively located on two opposite sides of the transparent window. The connection wires include first and second wire groups. The first wire group includes first connection wires. Each first connection wire has a first segment and a second segment. A first insulation layer is disposed between the first and second segments that are electrically connected to each other. The second wire group includes second connection wires. The first segments of the first connection wires and the second connection wires are overlapped, and the first insulation layer is disposed between the first segments of the first connection wires and the second connection wires.

公开(公告)号：US20200051480A1

公开(公告)日：2020-02-13

申请号：US16513737

申请日：2019-07-17

Applicant: Au Optronics Corporation

Inventor： Che-Chia Chang ,  Ming-Hung Chuang ,  Ming-Hsien Lee ,  Chun-Fu Chung

IPC: G09G3/20

Abstract: A display apparatus includes a plurality of pixel lines, a multiplexer, a first switch and a second switch. The pixel lines are respectively coupled to a plurality of data lines. The data lines include a first selected data line, a second selected data line and a plurality of other data lines. The first switch is coupled between the first selected data line and a first non-selected data line among the other data lines and is turned on or turned off according to a first control signal. The second switch is coupled between the first selected data line and a second non-selected data line among the other data lines and is turned on or cut off according to a second control signal.

公开(公告)号：US12118925B2

公开(公告)日：2024-10-15

申请号：US18243406

申请日：2023-09-07

Applicant: AU Optronics Corporation

Inventor： Che-Chia Chang ,  Shang-Jie Wu ,  Yu-Chieh Kuo ,  Hsien-Chun Wang ,  Sin-An Lin ,  Mei-Yi Li ,  Yu-Hsun Chiu ,  Ming-Hung Chuang ,  Yi-Jung Chen

IPC: G09G3/32 ,  G09G3/20

CPC classification number: G09G3/32 ,  G09G3/2007 ,  G09G2300/0809 ,  G09G2310/061 ,  G09G2310/067 ,  G09G2320/0233

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

公开(公告)号：US10950165B2

公开(公告)日：2021-03-16

申请号：US16534401

申请日：2019-08-07

Applicant: AU Optronics Corporation

Inventor： Che-Chia Chang ,  Ming-Hsien Lee ,  Chun-Fu Chung ,  Ming-Hung Chuang

IPC: G09G3/20

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

公开(公告)号：US10770013B2

公开(公告)日：2020-09-08

申请号：US16457934

申请日：2019-06-29

Applicant: Au Optronics Corporation

Inventor： Che-Chia Chang ,  Hsien-Chun Wang ,  Pin-Miao Liu ,  Ming-Hung Chuang ,  Ming-Hsien Lee ,  Shin-Shueh Chen

IPC: G09G5/10 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

公开(公告)号：US20180336861A1

公开(公告)日：2018-11-22

申请号：US15981900

申请日：2018-05-17

Applicant: Au Optronics Corporation

Inventor： Che-Chia Chang ,  Chun-Ru Huang ,  Ming-Hung Chuang

IPC: G09G3/36 ,  H01L27/12

Abstract: A display panel and a pixel circuit thereof are provided. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits. Each of the pixel circuits is coupled to corresponding gate line and data line. Each of the pixel circuits includes a first gate line and a pull-low switch. The first gate line is coupled to a control terminal of a driving transistor, and provides a first gate signal to drive the driving transistor during a driving time period. The pull-low switch pulls low the first gate signal to a reference low voltage according to a second gate signal on a second gate line when the driving time period finishes.

公开(公告)号：US11348509B2

公开(公告)日：2022-05-31

申请号：US17168452

申请日：2021-02-05

Applicant: AU Optronics Corporation

Inventor： Che-Chia Chang ,  Ming-Hsien Lee ,  Chun-Fu Chung ,  Ming-Hung Chuang

IPC: G09G3/20

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.