公开(公告)号：US10200037B2

公开(公告)日：2019-02-05

申请号：US15645446

申请日：2017-07-10

Applicant: Altera Corporation

Inventor： Srinivas Perisetty

IPC: H03K19/003 ,  H01L49/02 ,  H01L23/34

Abstract: A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.

公开(公告)号：US09496268B2

公开(公告)日：2016-11-15

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C11/412 ,  H01L27/11 ,  G11C7/10 ,  G11C5/06 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

公开(公告)号：US20170373690A1

公开(公告)日：2017-12-28

申请号：US15645446

申请日：2017-07-10

Applicant: Altera Corporation

Inventor： Srinivas Perisetty

IPC: H03K19/003 ,  H01L23/34

CPC classification number: H03K19/00369 ,  H01L23/34 ,  H01L28/00

Abstract: A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.

公开(公告)号：US20140258956A1

公开(公告)日：2014-09-11

申请号：US14281735

申请日：2014-05-19

Applicant: Altera Corporation

Inventor： David Lewis ,  Christopher Lane ,  Sarathy Partha Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy L. Lee

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。 控制电路耦合到非易失性存储器和配置存储器。 一组电压从控制电路的输出导出，并被应用于PLD内的电路。

公开(公告)号：US08750026B1

公开(公告)日：2014-06-10

申请号：US13923276

申请日：2013-06-20

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C11/412 ,  G11C7/10 ,  G11C8/16

CPC classification number: G11C11/412

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US20160232952A9

公开(公告)日：2016-08-11

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C7/10 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

公开(公告)号：US20150318029A1

公开(公告)日：2015-11-05

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C7/10 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。