公开(公告)号：US08331166B2

公开(公告)日：2012-12-11

申请号：US13036030

申请日：2011-02-28

Applicant: Cyrille Dray ,  Alexandre Ney

Inventor： Cyrille Dray ,  Alexandre Ney

IPC: G11C5/14

CPC classification number: G11C7/02 ,  G11C7/08 ,  G11C7/14 ,  G11C2207/002

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract translation: 提供了一种用于从存储器件中的存储单元读取的方法和系统。 在一个实施例中，存储器设备包括第一多个数据线和第二多个数据线，耦合到第一多个数据线和至少一个低参考线的至少一个第一多路复用器，耦合到 所述第二多个数据线和至少一个高参考线，耦合到所述至少一个第一多路复用器和所述至少一个第二多路复用器的至少一个第三多路复用器，以及耦合到所述至少一个第三多路复用器的参考存储器单元， 至少一个读出放大器。

公开(公告)号：US08644055B2

公开(公告)日：2014-02-04

申请号：US12963820

申请日：2010-12-09

Applicant: Alexandre Ney

Inventor： Alexandre Ney

IPC: G11C11/00

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

Abstract: This application describes embodiments of MRAM cells that utilize a PMOS transistor as an access transistor. The MRAM cells are configured to mitigate the effects of applying asymmetric current loads to transition a Magnetic-Tunnel Junction of the MRAM cell between magnetoresistive states.

Abstract translation: 本申请描述了利用PMOS晶体管作为存取晶体管的MRAM单元的实施例。 MRAM单元被配置为减轻施加不对称电流负载以在磁阻状态之间转换MRAM单元的磁隧道结的影响。

公开(公告)号：US08605479B2

公开(公告)日：2013-12-10

申请号：US12911603

申请日：2010-10-25

Applicant: Cyrille Dray ,  Alexandre Ney ,  Karl Hofmann

Inventor： Cyrille Dray ,  Alexandre Ney ,  Karl Hofmann

IPC: G11C5/06

CPC classification number: G11C11/1659 ,  G11C8/08 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C17/12 ,  G11C2213/74 ,  G11C2213/79

Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.

Abstract translation: 存储器件的代表性实现在存储器件的存储器单元之间具有晶体管。 存储器件可以被布置在存储器阵列中。 晶体管的使用可以包括交替地在存储器阵列中的存储器单元的对或组之间提供电隔离或电流路径。

公开(公告)号：US20120147663A1

公开(公告)日：2012-06-14

申请号：US12963820

申请日：2010-12-09

Applicant: Alexandre Ney

Inventor： Alexandre Ney

IPC: G11C11/15 ,  H01L29/82

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

Abstract: This application describes embodiments of MRAM cells that utilize a PMOS transistor as an access transistor. The MRAM cells are configured to mitigate the effects of applying asymmetric current loads to transition a Magnetic-Tunnel Junction of the MRAM cell between magnetoresistive states.

Abstract translation: 本申请描述了利用PMOS晶体管作为存取晶体管的MRAM单元的实施例。 MRAM单元被配置为减轻施加不对称电流负载以在磁阻状态之间转换MRAM单元的磁隧道结的影响。