公开(公告)号：US11978724B2

公开(公告)日：2024-05-07

申请号：US18145375

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H10B99/00

CPC classification number: H01L25/0657 ,  H01L21/02532 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L23/528 ,  H01L25/50 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H10B99/00 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US20250038152A1

公开(公告)日：2025-01-30

申请号：US18911798

申请日：2024-10-10

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US12170268B2

公开(公告)日：2024-12-17

申请号：US18614310

申请日：2024-03-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US11830804B2

公开(公告)日：2023-11-28

申请号：US16837948

申请日：2020-04-01

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Belgacem Haba ,  Stephen Morein ,  Ilyas Mohammed ,  Rajesh Katkar ,  Javier A. Delacruz

IPC: H01L23/50 ,  H01L23/367 ,  H01L21/48 ,  H01L23/64 ,  H01L23/49

CPC classification number: H01L23/50 ,  H01L21/4871 ,  H01L21/4889 ,  H01L23/367 ,  H01L23/49 ,  H01L23/642

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

公开(公告)号：US20240266326A1

公开(公告)日：2024-08-08

申请号：US18614310

申请日：2024-03-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H10B99/00

CPC classification number: H01L25/0657 ,  H01L21/02532 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L23/528 ,  H01L25/50 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H10B99/00 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US11621246B2

公开(公告)日：2023-04-04

申请号：US17107710

申请日：2020-11-30

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L29/66 ,  H01L25/065 ,  H01L29/08 ,  H01L23/528 ,  H01L29/45 ,  H01L21/8234 ,  H01L25/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/321 ,  H01L27/105

Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US20240347443A1

公开(公告)日：2024-10-17

申请号：US18381980

申请日：2023-10-19

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Belgacem Haba ,  Stephen Morein ,  Ilyas Mohammed ,  Rajesh Katkar ,  Javier A. Delacruz

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/367 ,  H01L23/49 ,  H01L23/64

CPC classification number: H01L23/50 ,  H01L21/4871 ,  H01L21/4889 ,  H01L23/367 ,  H01L23/49 ,  H01L23/642

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

公开(公告)号：US20230127020A1

公开(公告)日：2023-04-27

申请号：US18145375

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L25/065 ,  H01L29/08 ,  H01L23/528 ,  H01L29/45 ,  H01L21/8234 ,  H01L25/00 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L21/321 ,  H01L27/105

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.