公开(公告)号：US08829898B1

公开(公告)日：2014-09-09

申请号：US13154745

申请日：2011-06-07

Applicant: Yosef Solt ,  Asaf Idan ,  Ofer Benjamin ,  Eli Kurin

Inventor： Yosef Solt ,  Asaf Idan ,  Ofer Benjamin ,  Eli Kurin

IPC: G01N27/82

CPC classification number: G01R31/2879

Abstract: Aspects of the disclosure provide a method for testing. The method includes determining an electrical characteristic of an integrated circuit (IC), subjecting the IC to a stress test, characterizing the electrical characteristic of the IC subsequently to subjecting the IC to the stress test, and determining a quality attribute of the IC based on a comparison of the respective electrical characteristics of the IC before and after subjecting the IC to the stress test.

Abstract translation: 本公开的方面提供了一种测试方法。 该方法包括确定集成电路（IC）的电特性，对IC进行应力测试，表征IC随后对IC进行压力测试的电特性，以及基于以下步骤确定IC的质量属性： 在对IC进行应力测试之前和之后的IC的各个电特性的比较。

公开(公告)号：US08526255B1

公开(公告)日：2013-09-03

申请号：US13488981

申请日：2012-06-05

Applicant: Yosef Solt ,  Ofir Keren

Inventor： Yosef Solt ,  Ofir Keren

IPC: G11C7/00

CPC classification number: G11C29/26 ,  G11C29/10 ,  G11C2029/2602

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.

Abstract translation: 本公开的方面提供集成电路。 该集成电路包括：加扰器，被配置为基于用于使用存储器阵列的存储器配置向包络提供驱动地址和相关联的数据。 驱动地址和相关数据用于根据测试模式测试存储器阵列。 信封被配置为基于存储器配置将驾驶地址转换为存储器阵列的相应物理地址。

公开(公告)号：US06829245B1

公开(公告)日：2004-12-07

申请号：US09348351

申请日：1999-07-08

Applicant: Eitan Medina ,  David Shemla ,  Yosef Solt

Inventor： Eitan Medina ,  David Shemla ,  Yosef Solt

IPC: H04L1256

CPC classification number: H04L49/508 ,  H04L49/201 ,  H04L49/30 ,  H04L49/501

Abstract: A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.

Abstract translation: 一种网络交换机，包括多个输出端口，至少一个输入端口和排队管理器。 每个输出端口具有与其相关联的控制单元。 输入端口接收去往各种输出端口的输入数据。 排队管理器将传入的数据引导到其目标输出端口。 每个控制单元包括输出队列，丰满度/空虚传感器和行头（HOL）掩模。 输出队列存储发往其相关输出端口的输入数据。 传感器检测输出队列何时达到饱和或空虚状态。 当传感器感测到充满状态并且当传感器感测到空虚状态时，HOL掩模连接到传感器的输出并阻止输入数据流入输出队列。

公开(公告)号：US07689793B1

公开(公告)日：2010-03-30

申请号：US10809537

申请日：2004-03-24

Applicant: Yosef Solt ,  Sorel Horovitz

Inventor： Yosef Solt ,  Sorel Horovitz

IPC: G06F12/00

CPC classification number: G06F12/023

Abstract: A network switch may include a buffer management module to manage buffers in a buffer memory. The buffer management module may include an Allocation SRAM and a Reclaim SRAM. Each buffer in the buffer memory may be associated with a corresponding bit in the Allocation SRAM and Reclaim SRAM. A line including bits indicating available buffers in the Allocation SRAM may be written to the allocation register, and the buffer management module may allocate buffers from the allocation register. A reclaim module may age bits in the Reclaim SRAM. The reclaim module may reclaim buffers by searching corresponding lines in the Allocation SRAM and Reclaim SRAM and comparing the values of bits in the two lines.

Abstract translation: 网络交换机可以包括用于管理缓冲存储器中的缓冲器的缓冲器管理模块。 缓冲器管理模块可以包括分配SRAM和回收SRAM。 缓冲存储器中的每个缓冲器可以与分配SRAM和回收SRAM中的相应位相关联。 包括分配SRAM中指示可用缓冲器的位的行可以写入分配寄存器，并且缓冲器管理模块可以从分配寄存器分配缓冲区。 回收模块可能会使回收SRAM中的位变老。 回收模块可以通过在分配SRAM和回收SRAM中搜索相应的行来比较两行中的位的值来回收缓冲区。

公开(公告)号：US06988237B1

公开(公告)日：2006-01-17

申请号：US10752174

申请日：2004-01-06

Applicant: Yosef Solt ,  Eitan Joshua

Inventor： Yosef Solt ,  Eitan Joshua

IPC: G11C29/00

CPC classification number: G11C29/24 ,  G06F11/2215 ,  G11C29/42 ,  G11C2029/0405

Abstract: An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.

Abstract translation: 具有该方法的集成电路包括存储器，该存储器包括多条存储器线，每条存储线包括多个用于存储数据位的数据单元，以及多个纠错（EC）单元，用于存储 EC位对应于存储在存储器线的数据单元中的数据位; EC输入电路，用于基于相应的数据位产生EC位; EC输出电路，包括EC校正电路，以根据从存储器线的EC单元读取的位来校正从每个存储器线的数据单元读取的位中的错误; 以及开关，其包括从EC输入电路接收EC位的第一输入，用于从集成电路的EC测试节点接收测试EC位的第二输入，以及向存储器中的EC位或EC测试位提供EC位或EC测试位 按照测试信号。

公开(公告)号：US08572412B1

公开(公告)日：2013-10-29

申请号：US13015139

申请日：2011-01-27

Applicant: Yosef Solt

Inventor： Yosef Solt

IPC: G06F1/00

CPC classification number: G11C7/04 ,  G06F1/206 ,  G11C29/50

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes functional circuits configured to perform desired functions when a chip temperature is higher than a threshold, such as a room temperature. The IC chip includes a warm-up module configured to warm-up the IC chip in a warm-up mode to raise the chip temperature above the threshold. A method for warming up an IC chip prior to operation is also disclosed.

公开(公告)号：US08051348B1

公开(公告)日：2011-11-01

申请号：US12938066

申请日：2010-11-02

Applicant: Yosef Solt

Inventor： Yosef Solt

IPC: G01R31/28

CPC classification number: G01R31/31855

Abstract: An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.

Abstract translation: 集成电路包括包括第一和第二逻辑电路的逻辑电路以及被配置为测试逻辑电路的扫描链。 扫描链包括用于基于输入测试图案测试第一逻辑电路并输出第一输出测试图案的第一扫描链部分，用于选择并输出输入测试图案和第一输出测试图案之一的切换单元，作为 以及第二扫描链部分，用于基于来自切换单元的所选择的测试图案测试第二逻辑电路，并输出第二输出测试图案。 开关单元基于逻辑深度，门数，栅极输入的数量和逻辑电路的栅极输出的数量中的至少一个来选择输入测试图案和第一输出测试图案之一。

公开(公告)号：US07949908B2

公开(公告)日：2011-05-24

申请号：US11869308

申请日：2007-10-09

Applicant: Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

Inventor： Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11B20/1883 ,  G11C29/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

Abstract: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

Abstract translation: 自修复存储器系统包括包括存储器元件和冗余存储元件的存储器。 存储元件包括多个存储单元。 存储器修复模块识别非操作存储器单元并且选择至少一个包括非操作存储器单元的存储元件。 第一修复子电路通过用冗余存储器元件代替所选择的存储器元件来软地修复存储器。 第二修复子电路基于替换硬地修复存储器。

公开(公告)号：US20080091988A1

公开(公告)日：2008-04-17

申请号：US11869308

申请日：2007-10-09

Applicant: Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

Inventor： Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

IPC: G06F11/16

CPC classification number: G11B20/1883 ,  G11C29/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

Abstract: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

Abstract translation: 自修复存储器系统包括包括存储器元件和冗余存储元件的存储器。 存储元件包括多个存储单元。 存储器修复模块识别非操作存储器单元并且选择至少一个包括非操作存储器单元的存储元件。 第一修复子电路通过用冗余存储器元件代替所选择的存储器元件来软地修复存储器。 第二修复子电路基于替换硬地修复存储器。

公开(公告)号：US08423839B2

公开(公告)日：2013-04-16

申请号：US13113401

申请日：2011-05-23

Applicant: Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

Inventor： Reshef Bar Yoel ,  Yosef Solt ,  Michael Levi ,  Yosef Haviv

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11B20/1883 ,  G11C29/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

Abstract: A memory system includes an array of memory cells. The array of memory cells includes redundant memory cells. The redundant memory cells include at least two of a redundant row and a redundant column of memory cells. The repair module is configured to (i) identify at least two of a row and a column of the array of memory cells having non-operational memory cells and (ii) substitute the at least two of the row and the column of the array of memory cells with selected rows or columns of the redundant memory cells based on X predetermined sequences of substitutions. The repair module is configured to detect a failure in the array of memory cells that cannot be repaired using the X predetermined sequences of substitutions, and use an alternative repair sequence to repair the non-operational memory cells based on the detection of the failure.

Abstract translation: 存储器系统包括存储器单元阵列。 存储单元阵列包括冗余存储单元。 冗余存储器单元包括存储器单元的冗余行和冗余列中的至少两个。 修复模块被配置为（i）识别具有非操作存储器单元的存储器单元阵列的行和列中的至少两个，以及（ii）将阵列的阵列的行和列中的至少两个替换为 基于X预定的取代序列，具有冗余存储器单元的所选行或列的存储单元。 修复模块被配置为检测使用X预定的替换序列无法修复的存储器单元阵列中的故障，并且使用替代修复序列来基于故障的检测来修复非操作存储器单元。