公开(公告)号：US09685338B2

公开(公告)日：2017-06-20

申请号：US15242226

申请日：2016-08-19

Applicant: Transphorm Japan, Inc.

Inventor： Yuichi Minoura ,  Yoshitaka Watanabe

IPC: H01L21/28 ,  H01L29/40 ,  H02M3/28 ,  H01L29/66 ,  H01L29/78 ,  H01L23/29 ,  H01L29/778 ,  H01L29/20 ,  H01L23/31 ,  H02M3/335 ,  H02M7/04 ,  H02M1/00 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/28264 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/408 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H02M3/28 ,  H02M3/33576 ,  H02M7/04 ,  H02M2001/007 ,  H01L2924/00

Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.

公开(公告)号：US09231075B2

公开(公告)日：2016-01-05

申请号：US14645317

申请日：2015-03-11

Applicant: Transphorm Japan, Inc.

Inventor： Atsushi Yamada

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L21/56 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/56 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

公开(公告)号：US08773176B2

公开(公告)日：2014-07-08

申请号：US13730480

申请日：2012-12-28

Applicant: Transphorm Japan, Inc.

Inventor： Yasumori Miyazaki ,  Yoshihiro Takemae

IPC: H03K3/00

CPC classification number: H03K17/56 ,  H03K17/063 ,  H03K2217/0036

Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Abstract translation: 肖特基型晶体管的驱动电路包括提供有输入信号的输入端和连接到肖特基型晶体管的栅极的输出端。 在输入信号上升时，驱动电路将比肖特基式晶体管的击穿电压低的第一电压输出到输出端子，然后向连接到输出端子的电阻提供比击穿电压高的第二电压 。

公开(公告)号：US09620616B2

公开(公告)日：2017-04-11

申请号：US14582583

申请日：2014-12-24

Applicant: Transphorm Japan, Inc.

Inventor： Atsushi Yamada ,  Kenji Nukui

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42372 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787

Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.

公开(公告)号：US09136107B2

公开(公告)日：2015-09-15

申请号：US14098853

申请日：2013-12-06

Applicant: Transphorm Japan, Inc.

Inventor： Yoshiyuki Katani ,  Shinichi Akiyama

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/02112 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成电子传输层，在电子转移层上形成电子供给层，在电子供给层上形成覆盖层，在覆盖层上形成保护层，保护层 层，具有开口部，盖层的一部分露出，通过湿法在盖层的露出面上形成氧化膜。

公开(公告)号：US09099545B2

公开(公告)日：2015-08-04

申请号：US14034043

申请日：2013-09-23

Applicant: Transphorm Japan, Inc.

Inventor： Shinichi Akiyama ,  Kenji Nukui ,  Mutsumi Katou ,  Yoshitaka Watanabe ,  Tetsuya Itou ,  Yoichi Fujisawa ,  Toshiya Sato ,  Tsutomu Hosoda ,  Yuuichi Satou

IPC: H01L21/336 ,  H01L21/283 ,  H01L29/778 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/324 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

Abstract translation: 化合物半导体器件包括：衬底; 形成在所述基板上的化合物半导体层; 形成在所述化合物半导体层上的第一绝缘膜; 形成在所述第一绝缘膜上的第二绝缘膜; 以及栅电极，源电极和漏电极，各自形成在化合物半导体层上，其中栅电极由至少一栅极绝缘体填充有第一导电材料的第一开口形成，第一开口 形成在所述第一绝缘膜中并且被配置为部分地暴露所述化合物半导体层，并且其中所述源电极和所述漏电极由填充有至少第二导电材料的一对第二开口形成，并且所述第二开口形成在 至少所述第二绝缘膜和所述第一绝缘膜，并且被配置为部分地暴露所述化合物半导体层。

公开(公告)号：US09099351B2

公开(公告)日：2015-08-04

申请号：US13942773

申请日：2013-07-16

Applicant: Transphorm Japan, Inc.

Inventor： Masato Nishimori ,  Tadahiro Imada ,  Toshihiro Ohki

IPC: H01L29/78 ,  H01L29/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/12 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.

Abstract translation: 化合物半导体器件包括化合物半导体层：第一层; 形成在第一层上方的带隙比第一层大的第二层; 具有p型导电类型的第三层，形成在第二层上方; 经由第三层形成在第二层之上的栅电极; 形成为与第二层之上的第三层接触的与第二层相比更大的带隙的第四层; 以及与第四层相比带隙小的第五层，形成为与第四层上方的第三层接触。

公开(公告)号：US09035356B2

公开(公告)日：2015-05-19

申请号：US13942786

申请日：2013-07-16

Applicant: Transphorm Japan, Inc.

Inventor： Atsushi Yamada

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/30621 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  Y02B70/1483

Abstract: A semiconductor device includes an electron transit layer formed on a substrate; an electron supply layer formed on the electron transit layer; a doping layer formed on the electron supply layer, the doping layer being formed with a nitride semiconductor in which an impurity element to become p-type and C are doped; a p-type layer formed on the doping layer, the p-type layer being formed with a nitride semiconductor in which the impurity element to become p-type is doped; a gate electrode formed on the p-type layer; and a source electrode and a drain electrode formed on the doping layer or the electron supply layer. The p-type layer is formed in an area immediately below the gate electrode, and a density of the C doped in the doping layer is greater than or equal to 1×1017 cm−3 and less than or equal to 1×1019 cm−3.

Abstract translation: 半导体器件包括形成在衬底上的电子转移层; 形成在电子转移层上的电子供给层; 形成在所述电子供给层上的掺杂层，所述掺杂层由氮化物半导体形成，其中杂质元素成为p型和C掺杂; 形成在掺杂层上的p型层，p型层由掺杂有成为p型的杂质元素的氮化物半导体形成; 形成在p型层上的栅电极; 以及形成在掺杂层或电子供给层上的源电极和漏电极。 p型层形成在栅电极正下方的区域中，掺杂层中掺杂的C的密度大于或等于1×1017cm-3且小于或等于1×1019cm- 3。

公开(公告)号：US08957453B2

公开(公告)日：2015-02-17

申请号：US13954124

申请日：2013-07-30

Applicant: Transphorm Japan, Inc.

Inventor： Atsushi Yamada ,  Kenji Nukui

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42372 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787

Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.

Abstract translation: 制造半导体器件的方法包括依次在衬底上层叠形成电子迁移层，电子供给层，蚀刻停止层和p型膜，p型膜由氮化物半导体材料形成， 包括掺杂有p型杂质元素的Al，蚀刻停止层由包括GaN的材料形成，除去除了形成栅电极的区域之外的区域中的p型膜，通过干蚀刻 为了在要形成栅电极的区域中形成p型层，在干蚀刻中发生等离子体发射时进行干法蚀刻，干蚀刻开始后停止干蚀刻，源自 Al，并且在p型层上形成栅电极。

公开(公告)号：US08878571B2

公开(公告)日：2014-11-04

申请号：US14025506

申请日：2013-09-12

Applicant: Transphorm Japan, Inc.

Inventor： Yoshihiro Takemae

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/687

CPC classification number: H03K17/6877 ,  H03K17/04

Abstract: A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.

Abstract translation: 驱动器电路包括连接到肖特基晶体管的栅极的输出端子，以与肖特基晶体管相同的方式形成的参考晶体管，连接在第一电源线和参考晶体管的栅极之间的电阻器，电压发生器配置 提供具有等于或低于电阻器和参考晶体管之间的第一节点处的电压的电压的第二节点和被配置为响应于输入的信号将第二节点处的电压传输到输出端子的开关元件 到输入端子。