公开(公告)号：US08743634B2

公开(公告)日：2014-06-03

申请号：US13016071

申请日：2011-01-28

Applicant: Terence J. Magee ,  Cheng-Gang Kong

Inventor： Terence J. Magee ,  Cheng-Gang Kong

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.

Abstract translation: 一种用于使用通用低功率选通器来连接存储器控制器和源同步存储器的系统和方法。 可以通过选通连续的双速率时钟来生成一组双倍速率（2×）选通脉冲，以便仅在从控制器到存储器的数据传输的持续时间内使能一组双速率选通。 SDR连续单速率（1×）时钟域相对于存储器控制器的数据和控制可通过采用一组双速率选通进行采样，移动到一组双速率时钟域。 双速率选通组的相位可以相对于连续单速率时钟移位，并且可以通过改变一组双速率选通的相位来动态地切换所产生的同步信号与存储器的相位关系。 双速率时钟域的集合使每个位片被独立编程，以在相对于控制器单速率时钟的每个相位处产生到存储器的输出。

公开(公告)号：US20120195141A1

公开(公告)日：2012-08-02

申请号：US13016071

申请日：2011-01-28

Applicant: Terence J. Magee ,  Cheng-Gang Kong

Inventor： Terence J. Magee ,  Cheng-Gang Kong

IPC: G11C7/22

CPC classification number: G11C7/1072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.

Abstract translation: 一种用于使用通用低功率选通器来连接存储器控制器和源同步存储器的系统和方法。 可以通过选通连续的双速率时钟来生成一组双倍速率（2×）选通脉冲，以便仅在从控制器到存储器的数据传输的持续时间内使能一组双速率选通。 SDR连续单速率（1×）时钟域相对于存储器控制器的数据和控制可通过采用一组双速率选通进行采样，移动到一组双速率时钟域。 双速率选通组的相位可以相对于连续单速率时钟移位，并且可以通过改变一组双速率选通的相位来动态地切换所产生的同步信号与存储器的相位关系。 双速率时钟域的集合使每个位片被独立编程，以在相对于控制器单速率时钟的每个相位处产生到存储器的输出。

公开(公告)号：US08453096B2

公开(公告)日：2013-05-28

申请号：US13016472

申请日：2011-01-28

Applicant: Terence J. Magee ,  Christopher D. Paulson ,  Cheng-Gang Kong

Inventor： Terence J. Magee ,  Christopher D. Paulson ,  Cheng-Gang Kong

IPC: G06F17/50

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222

Abstract: A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.

Abstract translation: 用于延迟数据选通的非线性公共粗延迟系统和方法，以便保持精细的延迟精度并补偿PVT（过程，电压和温度）变化的影响。 普通粗延迟和精细延迟可以初始化为四分之一周期的延迟，用于移位与存储器件相关联的读输出DQS（数据队列选通），以便对物理层内的读输出DQ（数据队列）进行采样。 在每个延迟步骤中，精细延迟可以从最小到最大延迟编程为固定的线性增量，以便确定延迟的分辨率和精度。 基于应用最慢的操作频率，可以确定粗略和精细延迟的最佳延迟大小。 可以与备用精细延迟相关联地训练备用粗延迟和功能粗延迟，并且可以更新功能精细延迟以便监视过程，电压和温度变化效应。

公开(公告)号：US07605628B2

公开(公告)日：2009-10-20

申请号：US11745108

申请日：2007-05-07

Applicant: Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

Inventor： Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

IPC: H03H11/26

CPC classification number: H03K5/131 ,  H03K2005/00058 ,  H03K2005/00234

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract translation: 一种用于无毛刺更新标准单元的可编程延迟的方法，包括以下步骤：（A）响应于输入信号和多个第一控制信号产生输出信号，以及（B）产生多个第一控制信号 响应于输出信号和多个第二控制信号。 输出信号可以包括输入信号的延迟版本。 可以基于多个第一控制信号来确定输入信号和输出信号之间的延迟量。

公开(公告)号：US20120194248A1

公开(公告)日：2012-08-02

申请号：US13016472

申请日：2011-01-28

Applicant: Terence J. Magee ,  Christopher D. Paulson ,  Cheng-Gang Kong

Inventor： Terence J. Magee ,  Christopher D. Paulson ,  Cheng-Gang Kong

IPC: H03H11/26 ,  G01R29/00 ,  G06F19/00 ,  G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222

Abstract: A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.

Abstract translation: 用于延迟数据选通的非线性公共粗延迟系统和方法，以便保持精细的延迟精度并补偿PVT（过程，电压和温度）变化的影响。 普通粗延迟和精细延迟可以初始化为四分之一周期的延迟，用于移位与存储器件相关联的读输出DQS（数据队列选通），以便对物理层内的读输出DQ（数据队列）进行采样。 在每个延迟步骤中，精细延迟可以从最小到最大延迟编程为固定的线性增量，以便确定延迟的分辨率和精度。 基于应用最慢的操作频率，可以确定粗略和精细延迟的最佳延迟大小。 可以与备用精细延迟相关联地训练备用粗延迟和功能粗延迟，并且可以更新功能精细延迟以便监视过程，电压和温度变化效应。

公开(公告)号：US20080278210A1

公开(公告)日：2008-11-13

申请号：US11745108

申请日：2007-05-07

Applicant: Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

Inventor： Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

IPC: H03K5/13 ,  H03H11/26

CPC classification number: H03K5/131 ,  H03K2005/00058 ,  H03K2005/00234

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract translation: 一种用于无毛刺更新基于标准单元的可编程延迟的方法，包括以下步骤：（A）响应于输入信号和多个第一控制信号产生输出信号，以及（B）产生多个第一控制信号 响应于输出信号和多个第二控制信号。 输出信号可以包括输入信号的延迟版本。 可以基于多个第一控制信号来确定输入信号和输出信号之间的延迟量。

公开(公告)号：US07969799B2

公开(公告)日：2011-06-28

申请号：US12109643

申请日：2008-04-25

Applicant: Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

Inventor： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

IPC: G11C7/10 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC classification number: G11C7/1006

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Abstract translation: 包括一个或多个嵌入式输入/输出（I / O）缓冲器，一个或多个存储器接口硬件和控制逻辑的存储器接口物理层宏。 一个或多个嵌入式输入/输出（I / O）缓冲器支持多个I / O电源电压电平。 一个或多个存储器接口hardmacros耦合到一个或多个嵌入式I / O缓冲器。 控制逻辑控制一个或多个硬件和一个或多个I / O缓冲器。

公开(公告)号：US07865661B2

公开(公告)日：2011-01-04

申请号：US12250017

申请日：2008-10-13

Applicant: Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee

Inventor： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee

IPC: G06F12/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract translation: 包括写入逻辑和读取逻辑的存储器接口子系统。 写入逻辑可以被配置为将数据从存储器控制器传送到存储器。 读逻辑可以被配置为将数据从存储器传送到存储器控制器。 读取逻辑可以包括多个物理读取数据路径。 每个物理读取数据路径可以被配置为从存储器接收（i）读取数据信号的相应部分，（ii）与所接收的读取数据信号的相应部分相关联的相应读取数据选通信号，（iii） 门控信号，（iv）基本延迟信号和（v）偏移延迟信号。

公开(公告)号：US20090091987A1

公开(公告)日：2009-04-09

申请号：US12109643

申请日：2008-04-25

Applicant: Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

Inventor： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Abstract translation: 包括一个或多个嵌入式输入/输出（I / O）缓冲器，一个或多个存储器接口硬件和控制逻辑的存储器接口物理层宏。 一个或多个嵌入式输入/输出（I / O）缓冲器支持多个I / O电源电压电平。 一个或多个存储器接口hardmacros耦合到一个或多个嵌入式I / O缓冲器。 控制逻辑控制一个或多个硬件和一个或多个I / O缓冲器。

公开(公告)号：US20090043955A1

公开(公告)日：2009-02-12

申请号：US12250017

申请日：2008-10-13

Applicant: Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee

Inventor： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee

IPC: G06F12/06

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract translation: 包括写入逻辑和读取逻辑的存储器接口子系统。 写入逻辑可以被配置为将数据从存储器控制器传送到存储器。 读逻辑可以被配置为将数据从存储器传送到存储器控制器。 读取逻辑可以包括多个物理读取数据路径。 每个物理读取数据路径可以被配置为从存储器接收（i）读取数据信号的相应部分，（ii）与所接收的读取数据信号的相应部分相关联的相应读取数据选通信号，（iii） 门控信号，（iv）基本延迟信号和（v）偏移延迟信号。