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公开(公告)号:US20250166649A1
公开(公告)日:2025-05-22
申请号:US18515190
申请日:2023-11-20
Applicant: Realtek Semiconductor Corp.
Inventor: Yen-Hsun Chu , Yu-Che Kao
IPC: G10L21/0208 , G10L25/63
Abstract: The present invention provides a processing circuit of an electronic device including an audio/video content generation circuit, a user hotspot detection module and an output module is disclosed. The audio/video content generation circuit is configured to generate audio data and video data to a speaker and a display panel, respectively. The user hotspot detection module is configured to receive a microphone input from a microphone of the electronic device, and detect the microphone input to generate a user hotspot detection result when the speaker plays the audio data and the display panel shows the video data. The output module is configured to store the user hotspot detection result.
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公开(公告)号:US20250159106A1
公开(公告)日:2025-05-15
申请号:US18945795
申请日:2024-11-13
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor: KAI-HSIANG CHOU
Abstract: A collaborative operating system of audiovisual peripheral devices and an operating method thereof are provided. The system provides an audiovisual console, which includes an audiovisual processing unit, and a microcontroller, at least one connection interface, and a data-processing unit that implement a collaborative operation of the audiovisual peripheral devices. The audiovisual console connects with the peripheral device via the connection interface based on a communication protocol, and obtains a permission for accessing a camera and a microphone that are detected. The audiovisual console receives a video and an audio from the peripheral device based on the communication protocol. After the data-processing unit processes the video and the audio, the microcontroller generates and provides audiovisual data to the audiovisual processing unit. Accordingly, a display displays the video, and a speaker plays the audio, thereby allowing the audiovisual console that has no camera and microphone to hold a video conference.
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公开(公告)号:US20250147533A1
公开(公告)日:2025-05-08
申请号:US18817196
申请日:2024-08-27
Applicant: Realtek Semiconductor Corp.
Inventor: Yung-Chun Chang , Han-Chang Kang
IPC: G05F1/575
Abstract: A low-dropout (LDO) regulator and operation method thereof are provided. The LDO regulator may include a reference voltage generation circuit, an operational amplifier, a transistor and a multiphase configuration switching control circuit. The operation method may include: performing a first configuring operation to enable a first dedicated current path corresponding to a first phase to allow a target reference voltage used in LDO regulating mode to reach a first predetermined range after the first configuring operation is performed; performing a second configuring operation to enable a second dedicated current path corresponding to a second phase to allow the target reference voltage to reach a second predetermined range after the second configuring operation is performed; and performing a third configuring operation to allow the target reference voltage to be used as a reference voltage input into the operational amplifier in the LDO regulating mode after the third configuring operation is performed.
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公开(公告)号:US12277673B2
公开(公告)日:2025-04-15
申请号:US17697904
申请日:2022-03-17
Applicant: Realtek Semiconductor Corp.
Inventor: Chon Hou Sio , Chia-Wei Yu
IPC: G06T3/4046 , G06T5/20 , G06T5/73
Abstract: An image processing system includes: a first image processing device for performing a first image enhancement process on a source image to generate a first enhanced image; one or more second images processing device, each of which is used to perform a second image enhancement processing on a size-reduced image generated based on the source image, and accordingly to output one or more second enhanced images whose size identical to the source image; and an output controller for analyzing regional frequency characteristics of the source image to generate an analysis result, determining one or more region weights according to the analysis result, and synthesize the first enhanced image with the one or more second enhanced images according to the one or more region weights, thereby to generate an output image.
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公开(公告)号:US20250119835A1
公开(公告)日:2025-04-10
申请号:US18900123
申请日:2024-09-27
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor: Hou-Ji Dai
IPC: H04W52/02 , H04L49/109
Abstract: A wireless communication device and a power saving method are provided. The wireless communication device includes a wireless communication circuit, a system chip, a wake-up controller, and a beacon communication circuit. The system chip is electrically connected to the wireless communication circuit. The system chip is configured to successively make the wireless communication circuit and the system chip sleep in response to a power saving demand and configured to receive a wake-up signal to successively awake the system chip and the wireless communication circuit. The wake-up controller is electrically connected to the system chip. The wake-up controller is configured to send the wake-up signal to the system chip. The beacon communication circuit is electrically connected to the wake-up controller. The beacon communication circuit is configured to send a beacon packet periodically according to a transmission period.
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公开(公告)号:US12266421B2
公开(公告)日:2025-04-01
申请号:US18116823
申请日:2023-03-02
Applicant: Realtek Semiconductor Corp.
Inventor: Wen-Wei Lin , Ching-Sheng Cheng
IPC: G11C7/10
Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.
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公开(公告)号:US12262299B2
公开(公告)日:2025-03-25
申请号:US17839493
申请日:2022-06-14
Applicant: Realtek Semiconductor Corp.
Inventor: Chung-Yao Chang , Chuan-Hu Lin
Abstract: A method of switching an operation mode of a first multi-link device includes the first multi-link device establishing a plurality of links to a second multi-link device, and the first multi-link device determining according to a channel condition whether to receive a plurality of streams via the plurality of links or via one of the plurality of links.
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公开(公告)号:US20250085873A1
公开(公告)日:2025-03-13
申请号:US18824080
申请日:2024-09-04
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor: Kuo-Lun Huang , Shih-Han Lin
IPC: G06F3/06
Abstract: A memory control circuit includes an access control circuit, a connection pad circuit, and a pad control circuit. The connection pad circuit includes a transceiver circuit and a receiver circuit. The transceiver circuit and the receiver circuit are connected to a memory through an external pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes a read command, and receives data from the memory. The pad control circuit executes a write command or receives the data, the pad control circuit turns off the output of the receiver circuit. The access control circuit executes a power save command that the receiver circuit enters a power save mode. The pad control circuit decreases an operating current of the receiver circuit to minimum and forces an internal signal level of the receiver circuit. The receiver circuit enters a deep power save state.
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公开(公告)号:US12249989B1
公开(公告)日:2025-03-11
申请号:US18455676
申请日:2023-08-25
Applicant: Realtek Semiconductor Corp.
Inventor: Chia-Liang (Leon) Lin
Abstract: A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.
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公开(公告)号:US12229590B2
公开(公告)日:2025-02-18
申请号:US17211852
申请日:2021-03-25
Applicant: Realtek Semiconductor Corp.
Inventor: Jhe-Yi Lin , Chun-Kai Tseng , Wen-Yung Lee , Shau-Yu Cheng
IPC: G06F9/48 , G06F9/30 , G06F9/50 , G06F16/901
Abstract: A content channel generation device comprises a resource unit assignment circuit, for assigning scheduled station(s) as node(s) of a full binary tree according to a search algorithm; a node computing circuit, for determining first node connection information of the full binary tree, and to determine second node connection information of a smallest full binary tree according to a smallest binary tree algorithm and the first node connection information; a load balance circuit, for determining user field numbers corresponding to content channels according to a load balance function and the second node connection information; a user field generation circuit, for generating a traversal result of the smallest full binary tree according to a traversal algorithm and the second node connection information, and for generating user fields corresponding to the content channels according to the traversal result, to generate the content channels.
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