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    INVERTER-BASED COMPARATOR
    1.
    发明公开
    INVERTER-BASED COMPARATOR 审中-公开

    公开(公告)号：US20240235426A1

    公开(公告)日：2024-07-11

    申请号：US18095399

    申请日：2023-01-10

    Applicant: NCKU Research and Development Foundation ,  Himax Technologies Limited

    Inventor： Philex Ming-Yan Fan ,  Yi-Fu Chen ,  Bo-Rui Chen

    IPC: H02M7/5387 ,  H02M1/00 ,  H03K5/24

    CPC classification number: H02M7/53873 ,  H02M1/0032 ,  H03K5/2472

    Abstract: An inverter-based comparator, powered between a first supply voltage and a second supply voltage being lower than the first supply voltage, includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches. The first inverter branch and the second inverter branch are configured to compare an input voltage with an internal trigger point, thereby generating a compare voltage at an interconnected node. One of the at least two tuning switches is controlled to isolate the first supply voltage and another is controlled to isolate the second supply voltage to compensate for trigger point shifting.

    Boost converter with fast transient response
    2.
    发明授权
    Boost converter with fast transient response 有权

    公开(公告)号：US11569740B2

    公开(公告)日：2023-01-31

    申请号：US17204162

    申请日：2021-03-17

    Applicant: NCKU Research and Development Foundation ,  Himax Technologies Limited

    Inventor： Chun-Yen Chen ,  Chien-Hung Tsai ,  Chia-Hsuan Huang ,  Teng-Kuei Wu

    IPC: H02M3/156

    Abstract: A boost converter includes an inductor and a diode electrically connected in series between an input voltage and an output voltage; a transistor electrically coupled to an interconnected node of the inductor and the diode; and a controller that controls switching of the transistor according to a transient mode and an estimated load current. The output voltage in a light-to-heavy load transient mode has at least one first valley point with a value of a transient voltage threshold, followed by at least one second valley point with a value higher than the first valley point, before exiting the light-to-heavy load transient mode.

    All-MOSFET voltage reference circuit with stable bias current and reduced error
    3.
    发明授权
    All-MOSFET voltage reference circuit with stable bias current and reduced error 有权

    公开(公告)号：US11320851B1

    公开(公告)日：2022-05-03

    申请号：US17109801

    申请日：2020-12-02

    Applicant: NCKU Research and Development Foundation ,  Himax Technologies Limited

    Inventor： Wei-Ting Yeh ,  Chien-Hung Tsai

    IPC: G05F3/26 ,  G05F1/445 ,  G05F1/46

    Abstract: An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

    ARTIFICIAL NEURAL NETWORK REGULARIZATION SYSTEM FOR A RECOGNITION DEVICE AND A MULTI-STAGE TRAINING METHOD ADAPTABLE THERETO
    5.
    发明申请
    ARTIFICIAL NEURAL NETWORK REGULARIZATION SYSTEM FOR A RECOGNITION DEVICE AND A MULTI-STAGE TRAINING METHOD ADAPTABLE THERETO 审中-公开

    公开(公告)号：US20200334555A1

    公开(公告)日：2020-10-22

    申请号：US16386784

    申请日：2019-04-17

    Applicant: NCKU Research and Development Foundation ,  Himax Technologies Limited

    Inventor： Tzu-Shiuan Liu ,  Ming-Der Shieh

    IPC: G06N5/04 ,  G06N3/08 ,  G06N3/04 ,  G06N20/20

    Abstract: An artificial neural network regularization system for a recognition device includes an input layer generating an initial feature map of an image; a plurality of hidden layers convoluting the initial feature map to generate an object feature map; and a matching unit receiving the object feature map and performing matching accordingly to output a recognition result. A first inference block and a second inference block are disposed in at least one hidden layer of an artificial neural network. The first inference block is turned on and the second inference block is turned off in first mode, in which the first inference block receives only output of preceding-layer first inference block. The first inference block and the second inference block are turned on in second mode, in which the second inference block receives output of preceding-layer second inference block and output of preceding-layer first inference block.

    Clock and data recovery circuit with bidirectional frequency detection and electronic device using the same
    9.
    发明授权
    Clock and data recovery circuit with bidirectional frequency detection and electronic device using the same 有权
    时钟和数据恢复电路具有双向频率检测和电子设备使用相同

    公开(公告)号：US09559705B1

    公开(公告)日：2017-01-31

    申请号：US14953041

    申请日：2015-11-27

    Applicant: NCKU RESEARCH AND DEVELOPMENT FOUNDATION ,  HIMAX TECHNOLOGIES LIMITED

    Inventor： Soon-Jyh Chang ,  Yen-Long Lee ,  Chung-Ming Huang ,  Yen-Chi Chen

    IPC: H03L7/08 ,  H03L7/18 ,  H03L7/087 ,  H03L7/099 ,  H04L7/00 ,  H04L12/26

    CPC classification number: H03L7/0807 ,  H03L7/07 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/06 ,  H04L7/0083 ,  H04L7/033

    Abstract: A clock and data recovery (CDR) circuit is provided. A phase detection circuit receives an input signal and a clock signal to output a first voltage signal. A first comparing circuit determines whether the first voltage signal is within a voltage range to output a first up signal and a first down signal. A counting circuit updates a counting value according to the input signal and the clock signal. A second comparing circuit determines whether the counting value is within a value range to output a second up signal and a second down signal. A selection circuit outputs a second voltage signal according to the first up signal, the first down signal, the second up signal, and the second down signal. A voltage controlled oscillator outputs the clock signal according to the first voltage signal and the second voltage signal.

    Abstract translation: 提供时钟和数据恢复（CDR）电路。 相位检测电路接收输入信号和时钟信号以输出第一电压信号。 第一比较电路确定第一电压信号是否在电压范围内，以输出第一上升信号和第一下降信号。 计数电路根据输入信号和时钟信号更新计数值。 第二比较电路确定计数值是否在输出第二上升信号和第二下降信号的值范围内。 选择电路根据第一上升信号，第一下降信号，第二上升信号和第二下降信号输出第二电压信号。 压控振荡器根据第一电压信号和第二电压信号输出时钟信号。

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