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    CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES
    1.
    发明申请
    CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES 有权
    高级设备技术的电容提取

    公开(公告)号：US20130191798A1

    公开(公告)日：2013-07-25

    申请号：US13357544

    申请日：2012-01-24

    Applicant: Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    Inventor： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036

    Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

    Abstract translation: 接收到设计集成电路的技术特定信息。 创建了用于捕获集成电路电容的多个规范层次模型。 多个规范层级模型至少包括一个规范模型，用于捕获具有多个导体的装置的电容，以及规范模型，用于捕获装置的至少一部分与集成的装置的一个或多个其它导体之间的电容 电路。 规范层次模型可以应用于集成电路的布局。 布局的电容可以基于规范层次模型来确定。

    Method and system for parallel processing of IC design layouts
    4.
    发明授权
    Method and system for parallel processing of IC design layouts 失效
    IC设计布局并行处理方法与系统

    公开(公告)号：US07657856B1

    公开(公告)日：2010-02-02

    申请号：US11520487

    申请日：2006-09-12

    Applicant: Mathew Koshy ,  Roland Ruehl ,  Min Cao ,  Li-Ling Ma ,  Eitan Cadouri ,  Tianhao Zhang

    Inventor： Mathew Koshy ,  Roland Ruehl ,  Min Cao ,  Li-Ling Ma ,  Eitan Cadouri ,  Tianhao Zhang

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

    Abstract translation: 公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。 在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中执行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。 一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

    System and method for random defect yield simulation of chip with built-in redundancy
    6.
    发明授权
    System and method for random defect yield simulation of chip with built-in redundancy 有权
    具有内置冗余的芯片的随机缺陷产量仿真的系统和方法

    公开(公告)号：US07984399B1

    公开(公告)日：2011-07-19

    申请号：US11965681

    申请日：2007-12-27

    Applicant: Roland Ruehl ,  Mathew Koshy ,  Jonathan Fales ,  Udayan Gumaste

    Inventor： Roland Ruehl ,  Mathew Koshy ,  Jonathan Fales ,  Udayan Gumaste

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5068

    Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

    Abstract translation: 在随机缺陷产量模拟中，特定的缺陷尺寸与特定的物理设计相互作用并具有与之相关联的故障的故障概率。 故障模型是以故障概率为依据的。 它提供了具有内置冗余方案的芯片的随机缺陷产量模拟问题的解决方案。 该解决方案首先通过内置冗余方案定义了芯片的独立故障模式，并有效地模拟了每种模式。 然后，它可以根据芯片的架构累积各自的故障概率。

    System and method for using rules-based analysis to enhance models-based analysis
    7.
    发明授权
    System and method for using rules-based analysis to enhance models-based analysis 有权
    使用基于规则的分析来加强基于模型的分析的系统和方法

    公开(公告)号：US07886243B1

    公开(公告)日：2011-02-08

    申请号：US11965685

    申请日：2007-12-27

    Applicant: Udayan Gumaste ,  Roland Ruehl ,  Mathew Koshy ,  Harsh Deshmane

    Inventor： Udayan Gumaste ,  Roland Ruehl ,  Mathew Koshy ,  Harsh Deshmane

    IPC: G06F17/50 ,  G06F9/45

    CPC classification number: G06F17/5081

    Abstract: The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify specific areas of a layout that can then be analyzed in detail using models. This approach provides numerous advantages. It allows the models-based analysis tool to concentrate upon portions of the layout that requires greater attention and allocate fewer resources towards the areas less critical to the yield.

    Abstract translation: 本发明提出了一种集成了基于规则的方法和基于模型的方法的可制造性分析的混合方法。 例如，可以使用基于规则的分析来优化基于模型的分析的性能。 规则分析可用于识别布局的特定区域，然后可以使用模型详细分析。 这种方法提供了许多优点。 它允许基于模型的分析工具集中在需要更多关注的部分布局上，并将更少的资源分配给对产量不太关键的区域。

    Capacitance extraction for advanced device technologies
    8.
    发明授权
    Capacitance extraction for advanced device technologies 有权
    高级器件技术的电容提取

    公开(公告)号：US08522181B2

    公开(公告)日：2013-08-27

    申请号：US13357544

    申请日：2012-01-24

    Applicant: Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    Inventor： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036

    Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

    Abstract translation: 接收到设计集成电路的技术特定信息。 创建了用于捕获集成电路电容的多个规范层次模型。 多个规范层级模型至少包括一个规范模型，用于捕获具有多个导体的装置的电容，以及规范模型，用于捕获装置的至少一部分与集成的装置的一个或多个其它导体之间的电容 电路。 规范层次模型可以应用于集成电路的布局。 布局的电容可以基于规范层次模型来确定。

    Method and system for parallel processing of IC design layouts
    9.
    发明授权
    Method and system for parallel processing of IC design layouts 有权
    IC设计布局并行处理方法与系统

    公开(公告)号：US08448096B1

    公开(公告)日：2013-05-21

    申请号：US11479600

    申请日：2006-06-30

    Applicant: Xiaojun Wang ,  Roland Ruehl ,  Li-Ling Ma ,  Mathew Koshy ,  Tianhao Zhang ,  Udayan Gumaste ,  Krzysztof Antoni Kozminski ,  Haifang Liao ,  Xinming Tu ,  Xu Zhu

    Inventor： Xiaojun Wang ,  Roland Ruehl ,  Li-Ling Ma ,  Mathew Koshy ,  Tianhao Zhang ,  Udayan Gumaste ,  Krzysztof Antoni Kozminski ,  Haifang Liao ,  Xinming Tu ,  Xu Zhu

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/04

    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

    Abstract translation: 公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。 在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中进行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。 一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

    System and method for model-based scoring and yield prediction
    10.
    发明授权
    System and method for model-based scoring and yield prediction 有权
    用于基于模型的评分和产量预测的系统和方法

    公开(公告)号：US07689948B1

    公开(公告)日：2010-03-30

    申请号：US11678593

    申请日：2007-02-24

    Applicant: David White ,  Roland Ruehl ,  Mathew Koshy

    Inventor： David White ,  Roland Ruehl ,  Mathew Koshy

    IPC: G06F17/50 ,  G06F19/00 ,  G01R31/02 ,  G06F11/00

    CPC classification number: G06F17/504 ,  G06F2217/10 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured for performing at least predicting a physical realization of a layout design based at least in part on one or more model parameters, determining one or more hotspots associated with the layout design, determining a score for each of the one or more hotspots associated with the layout design, and categorizing the one or more hotspots according to at least the score in some embodiments. In some embodiments, the methods or the systems further use at least one processor for the act of determining one or more hotspots by using at least the design intent or the manufacturing information.

    Abstract translation: 用于整合模型和准确预测以评估电路设计的方法和系统，其转化为更精确和更不复杂的产量预测。 在本发明的方法中，计算机实现的方法和系统使用至少一个处理器，其被配置为至少部分地基于一个或多个模型参数来执行至少预测布局设计的物理实现，确定一个或多个热点 与布局设计相关联，确定与布局设计相关联的一个或多个热点中的每一个的分数，以及在一些实施例中至少根据分数对一个或多个热点进行分类。 在一些实施例中，方法或系统进一步使用至少一个处理器来通过至少使用设计意图或制造信息来确定一个或多个热点的动作。

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