公开(公告)号：US08330209B2

公开(公告)日：2012-12-11

申请号：US13069710

申请日：2011-03-23

Applicant: Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

Inventor： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract translation: 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

公开(公告)号：US07906807B2

公开(公告)日：2011-03-15

申请号：US12827069

申请日：2010-06-30

Applicant: Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  Kuo-Tung Chang ,  Huaqiang Wu

Inventor： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  Kuo-Tung Chang ,  Huaqiang Wu

IPC: H01L29/92 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Abstract translation: 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。 与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

公开(公告)号：US20100264480A1

公开(公告)日：2010-10-21

申请号：US12827069

申请日：2010-06-30

Applicant: Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T Chang ,  Huaqiang Wu

Inventor： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T Chang ,  Huaqiang Wu

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Abstract translation: 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。 与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

公开(公告)号：US07381391B2

公开(公告)日：2008-06-03

申请号：US11650569

申请日：2007-01-05

Applicant: Michael G. Spencer ,  Francis J. DiSalvo ,  Huaqiang Wu

Inventor： Michael G. Spencer ,  Francis J. DiSalvo ,  Huaqiang Wu

IPC: C01B21/064 ,  C01B21/06 ,  C01B21/072

CPC classification number: C01B21/0632 ,  C01B21/06 ,  C01B21/064 ,  C01B21/0722 ,  C01P2002/52 ,  C01P2002/54 ,  C01P2002/72 ,  C01P2002/82 ,  C01P2002/84 ,  C01P2004/03 ,  C01P2004/20 ,  C01P2004/22 ,  C01P2004/61 ,  C01P2004/62 ,  C01P2006/80 ,  C30B9/00 ,  C30B29/406

Abstract: The present invention provides compositions and a novel high-yielding process for preparing high purity Group III nitrides. The process involves heating a Group III metal and a catalytic amount of a metal wetting agent in the presence of a nitrogen source. Group III metals can be stoichiometrically converted into high purity Group III nitride powders in a short period of time. The process can provide multi-gram quantities of high purity Group III nitrides in relatively short reaction times. Detailed characterizations of GaN powder were preformed and are reported herein, including morphology and structure by SEM and XRD, optical properties by cathodoluminescence (CL), and Raman spectra to determine the quality of the GaN particles. The purity of GaN powder was found to be greater than 99.9% pure, as analyzed by Glow Discharge Mass Spectrometry (GDMS). Green, yellow, and red light emission can be obtained from doped GaN powders.

Abstract translation: 本发明提供组合物和用于制备高纯度III族氮化物的新型高产方法。 该方法包括在氮源的存在下加热第III族金属和催化量的金属润湿剂。 III族金属可以在短时间内化学计量地转化为高纯度III族氮化物粉末。 该方法可以在相对短的反应时间内提供多克数量的高纯度III族氮化物。 进行GaN粉末的详细表征，并在本文中报道，包括通过SEM和XRD的形态和结构，通过阴极发光（CL）的光学性质和拉曼光谱来确定GaN颗粒的质量。 通过辉光放电质谱（GDMS）分析，发现GaN粉末的纯度大于99.9％纯度。 可以从掺杂的GaN粉末获得绿色，黄色和红色发光。

公开(公告)号：US09245895B2

公开(公告)日：2016-01-26

申请号：US13190565

申请日：2011-07-26

Applicant: Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

Inventor： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC: H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Abstract translation: 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US08653581B2

公开(公告)日：2014-02-18

申请号：US12342016

申请日：2008-12-22

Applicant: Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

Inventor： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

IPC: H01L27/115

CPC classification number: H01L29/792 ,  G11C16/3427 ,  H01L21/26586 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7923

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract translation: 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

公开(公告)号：US07569206B2

公开(公告)日：2009-08-04

申请号：US12060749

申请日：2008-04-01

Applicant: Michael G. Spencer ,  Francis J. DiSalvo ,  Huaqiang Wu

Inventor： Michael G. Spencer ,  Francis J. DiSalvo ,  Huaqiang Wu

IPC: C01B21/06

CPC classification number: C01B21/0632 ,  C01B21/06 ,  C01B21/064 ,  C01B21/0722 ,  C01P2002/52 ,  C01P2002/54 ,  C01P2002/72 ,  C01P2002/82 ,  C01P2002/84 ,  C01P2004/03 ,  C01P2004/20 ,  C01P2004/22 ,  C01P2004/61 ,  C01P2004/62 ,  C01P2006/80 ,  C30B9/00 ,  C30B29/406

Abstract: The present invention provides compositions and a novel high-yielding process for preparing high purity Group III nitrides. The process involves heating a Group III metal and a catalytic amount of a metal wetting agent in the presence of a nitrogen source. Group III metals can be stoichiometrically converted into high purity Group III nitride powders in a short period of time. The process can provide multi-gram quantities of high purity Group III nitrides in relatively short reaction times. Detailed characterizations of GaN powder were performed and are reported herein, including morphology and structure by SEM and XRD, optical properties by cathodoluminescence (CL), and Raman spectra to determine the quality of the GaN particles. The purity of GaN powder was found to be greater than 99.9% pure, as analyzed by Glow Discharge Mass Spectrometry (GDMS). Green, yellow, and red light emission can be obtained from doped GaN powders.

Abstract translation: 本发明提供组合物和用于制备高纯度III族氮化物的新型高产方法。 该方法包括在氮源的存在下加热第III族金属和催化量的金属润湿剂。 III族金属可以在短时间内化学计量地转化为高纯度III族氮化物粉末。 该方法可以在相对短的反应时间内提供多克数量的高纯度III族氮化物。 进行GaN粉末的详细表征，并在本文中报道，包括通过SEM和XRD的形态和结构，通过阴极发光（CL）的光学性质和拉曼光谱来确定GaN颗粒的质量。 通过辉光放电质谱（GDMS）分析，发现GaN粉末的纯度大于99.9％纯度。 可以从掺杂的GaN粉末获得绿色，黄色和红色发光。

公开(公告)号：US20090108330A1

公开(公告)日：2009-04-30

申请号：US11924169

申请日：2007-10-25

Applicant: Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

Inventor： Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

IPC: H01L29/792 ,  H01L21/3205

CPC classification number: H01L29/7923 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11568

Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract translation: 提供了包含半导体衬底上的两个分裂子光刻电荷存储节点的存储单元以及用于制造存储单元的方法。 这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。 通过在间隔物的倾斜侧表面或外表面之间除去第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。 此外，通过去除间隔物的倾斜侧表面或外表面之间的电荷存储层的暴露部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个分裂的亚光刻电荷存储节点。

公开(公告)号：US20090061631A1

公开(公告)日：2009-03-05

申请号：US11848515

申请日：2007-08-31

Applicant: Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

Inventor： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

IPC: H01L21/311

CPC classification number: H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Abstract translation: 提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。 该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。 可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

公开(公告)号：US20070178671A1

公开(公告)日：2007-08-02

申请号：US11541919

申请日：2006-10-02

Applicant: Michael Spencer ,  Phani Konkapaka ,  Huaqiang Wu ,  Yuri Makarov

Inventor： Michael Spencer ,  Phani Konkapaka ,  Huaqiang Wu ,  Yuri Makarov

IPC: H01L21/20 ,  H01L21/36 ,  H01L31/20

CPC classification number: C30B25/00 ,  C30B23/00 ,  C30B29/40 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L31/184

Abstract: GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes place. In one embodiment, the inert gas is N2, and the powder source is GaN powder that is loaded into source chambers. The GaN powder is congruently evaporated into Ga and N2 vapors at temperatures between approximately 1000 and 1200° C. The formation of Ga liquid in the powder is suppressed by the purging of an inert gas through the powder. The poser may also be isolated from a nitride containing gas provided at the growth cite. In one embodiment, the inert gas is flowed through the powder.

Abstract translation: 通过从粉末中产生Ga蒸气并使用来自源的惰性吹扫气体将蒸汽输送到发生GaN生长的生长位置来生长GaN。 在一个实施方案中，惰性气体是N 2，并且粉末源是装载到源室中的GaN粉末。 在约1000-1200℃的温度下，GaN粉末一致地蒸发成Ga和N 2 H 2蒸汽。通过粉末中的惰性气体的吹扫来抑制粉末中的Ga液的形成。 该位置也可以与生长引起的含氮气体隔离。 在一个实施方案中，惰性气体流过粉末。