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    Semiconductor device and method for manufacturing the same
    1.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08896051B2

    公开(公告)日：2014-11-25

    申请号：US13601061

    申请日：2012-08-31

    Applicant: Hiroyuki Nansei

    Inventor： Hiroyuki Nansei

    IPC: H01L29/792 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28

    CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: According to one embodiment, a semiconductor device includes a lower layer connection object, a stacked body, an insulating film, and a via. The stacked body has a plurality of insulating layers and a plurality of electrode layers alternately stacked on the lower layer connection object. The stacked body has a staircase structure unit. The via connects uppermost electrode layer at each step of the staircase structure unit and the lower layer connection object through the via hole. The via has an upper part provided on and in contact with a top face of the uppermost electrode layer, and a penetrating part provided to be thinner than the upper part inside the insulating film in the via hole. The penetrating part connects the upper part and the lower layer connection object.

    Abstract translation: 根据一个实施例，半导体器件包括下层连接对象，层叠体，绝缘膜和通孔。 层叠体具有交替层叠在下层连接体上的多个绝缘层和多个电极层。 堆叠体具有楼梯结构单元。 通孔通过通孔在楼梯结构单元的每个台阶和下层连接物上连接最上层的电极层。 通孔具有设置在最上面的电极层的顶面并与之接触的上部，以及设置成比通孔中的绝缘膜内部的上部更薄的穿透部。 穿透部分连接上部和下层连接物体。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130228848A1

    公开(公告)日：2013-09-05

    申请号：US13601061

    申请日：2012-08-31

    Applicant: Hiroyuki NANSEI

    Inventor： Hiroyuki NANSEI

    IPC: H01L29/792 ,  H01L21/28

    CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: According to one embodiment, a semiconductor device includes a lower layer connection object, a stacked body, an insulating film, and a via. The stacked body has a plurality of insulating layers and a plurality of electrode layers alternately stacked on the lower layer connection object. The stacked body has a staircase structure unit. The via connects uppermost electrode layer at each step of the staircase structure unit and the lower layer connection object through the via hole. The via has an upper part provided on and in contact with a top face of the uppermost electrode layer, and a penetrating part provided to be thinner than the upper part inside the insulating film in the via hole. The penetrating part connects the upper part and the lower layer connection object.

    Abstract translation: 根据一个实施例，半导体器件包括下层连接对象，层叠体，绝缘膜和通孔。 层叠体具有交替层叠在下层连接体上的多个绝缘层和多个电极层。 堆叠体具有楼梯结构单元。 通孔通过通孔在楼梯结构单元的每个台阶和下层连接物上连接最上层的电极层。 通孔具有设置在最上面的电极层的顶面并与之接触的上部，以及设置成比通孔中的绝缘膜内部的上部更薄的穿透部。 穿透部分连接上部和下层连接物体。

    METHOD OF MANUFACTURING ELECTRONIC COMPONENT
    4.
    发明申请
    METHOD OF MANUFACTURING ELECTRONIC COMPONENT 有权
    制造电子元件的方法

    公开(公告)号：US20110070713A1

    公开(公告)日：2011-03-24

    申请号：US12882649

    申请日：2010-09-15

    Applicant: Hiroyuki Nansei

    Inventor： Hiroyuki Nansei

    IPC: H01L21/02

    CPC classification number: H01L45/16 ,  H01L27/0207 ,  H01L27/24

    Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.

    Abstract translation: 根据一个实施例，通过使用侧壁转移工艺形成下部布线层，所述侧壁转移工艺用于形成具有沿牺牲或虚拟图案的侧壁的闭环的侧壁膜，并且在去除牺牲图案以离开侧壁膜之后，选择性地去除 该基材以侧壁膜为掩模。 使用侧壁转移工艺，通过另一层在下布线层的上层中形成一个或多个上布线层。 共同进行用于切割下布线层和上布线层的蚀刻，由此对下布线层和上布线层施加闭环切割。

    Non-volatile memory and method of controlling the same
    6.
    发明授权
    Non-volatile memory and method of controlling the same 有权
    非易失性存储器及其控制方法

    公开(公告)号：US07274592B2

    公开(公告)日：2007-09-25

    申请号：US11342947

    申请日：2006-01-30

    Applicant: Yukio Hayakawa ,  Hiroyuki Nansei

    Inventor： Yukio Hayakawa ,  Hiroyuki Nansei

    IPC: G11C16/04

    CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

    Abstract: A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the region surrounded by the word line and the bit lines. A bias is applied to one of the plug-like control electrodes and the word line so that the portion on the surface of the semiconductor substrate that is located immediately below the word line and corresponds to the location of the bias-applied control electrode is put into an accumulation state or a depletion state. In this manner, the width of the channel is adjusted, and the charge holding state of each of the four charge accumulation regions is controlled through the channel width adjustment.

    Abstract translation: 在两个位线交叉一个字线的区域中设置具有由ONO膜形成的栅极绝缘膜的单电池。 单个单元是四位多值单元，并具有四个电荷累积区。 在由字线和位线包围的区域中设置两个插塞状控制电极。 对一个插塞状控制电极和字线施加偏压，使得位于字线正下方并对应于施加偏压的控制电极的位置的半导体衬底的表面上的部分被放置 成为累积状态或耗尽状态。 以这种方式，调节通道的宽度，并且通过通道宽度调节来控制四个电荷累积区域中的每一个的电荷保持状态。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非挥发性半导体存储器件及制造非易失性半导体存储器件的方法

    公开(公告)号：US20110210301A1

    公开(公告)日：2011-09-01

    申请号：US12883593

    申请日：2010-09-16

    Applicant: Hiroyuki NANSEI

    Inventor： Hiroyuki NANSEI

    IPC: H01L45/00 ,  H01L21/02

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

    Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.

    Abstract translation: 根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 多条第一行; 多条第二线; 以及多个非易失性存储单元，其布置在所述多个第一线与所述多条第二线相交的位置处，其中所述多个非易失性存储单元中的每一个包括电阻变化元件和整流元件， 电阻变化元件和连续延伸在多条第二线上的电阻变化膜配置在多条第一线和多条第二线之间，电阻变化元件包括第一线与第二线相交的部分 在电阻变化膜。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 有权
    半导体器件及其制造方法

    公开(公告)号：US20090085213A1

    公开(公告)日：2009-04-02

    申请号：US12199690

    申请日：2008-08-27

    Applicant: Masahiko HIGASHI ,  Hiroyuki Nansei

    Inventor： Masahiko HIGASHI ,  Hiroyuki Nansei

    IPC: H01L23/52

    CPC classification number: H01L27/105 ,  H01L21/26586 ,  H01L27/11534 ,  H01L27/11568

    Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.

    Abstract translation: 半导体存储器件采用SONOS型存储器架构，并且在其中埋入导电膜的浅沟槽沟槽中包括位线扩散层。 这使得可以在不扩大半导体衬底的主表面上的面积的情况下降低位线扩散层的电阻率，并且制造具有稳定的电特性的半导体存储器件而不扩大单元面积。 位线通过将离子注入到Si 3 N 4的侧壁中而形成。

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