Invention Grant
- Patent Title: Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features
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Application No.: US15248985Application Date: 2016-08-26
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Publication No.: US09935635B2Publication Date: 2018-04-03
- Inventor: Jae-Hyeong Kim , Chih Tseng , Patrick Chuang
- Applicant: GSI Technology, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: GSI Technology, Inc.
- Current Assignee: GSI Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: DLA Piper LLP US
- Agent Nicholas Panno
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K19/0185
Abstract:
A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.
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