The present invention relates to a technology enabling a normal access by controlling a read access through an arbiter in a circuit for controlling an access to memory to which clock signals are input through two ports, respectively for a read access to a single port memory. The present invention includes an arbiter that generates an internal clock signal through a state transition among a first state for generating a first clock signal, a second state for generating a second clock signal, a standby state and a neutral state when generating the internal clock signal for reading data from the memory on the basis of the first clock signal and the second clock signal, and a read end signal that is supplied from the memory.